Memory Access Overview

In order to understand the meaning of the various timings on RAM, we need to first look at how memory is accessed. This is still only part of the overall memory subsystem, but it is the portion that relates directly to the memory timings. We will cover the remaining portions of memory access in a moment. Ignoring how a memory request actually gets to the RAM modules, then, the pattern for a memory access is as follows.

First, the requested address arrives at the memory module. In a worst case scenario, the address is not contained in one of the currently active rows of memory (also called memory pages), so an active row is flushed out, the new row is requested, the row becomes active, and after a slight delay, the specific column in the row can be requested. There is another delay while the column is accessed, and then the data begins coming across the memory bus. The whole column is not sent across the bus immediately, but is sent in several bursts instead. The number of bursts used in transmitting the data is referred to as the burst length, and these bursts occur at the effective data rate - i.e. two bits per clock on DDR/DDR2 and one bit per clock for SDRAM.

That is a worst case scenario, but luckily, that is not the most common occurrence. Due to spatial locality - which says that if you access one piece of data at address X, you will likely also access the data at X+1, X-1, X+2, X-2, etc. - memory has what is called active rows/pages. These are rows that are stored currently in what amounts to a small cache on the memory chips - this is called a "sense amplifier" - and when a request arrives for data that is already stored in an active row, only the request for a specific column is needed. Row sizes are typically 1KB or 2KB on current DRAMs and column sizes vary according to several other factors such as device width and burst length.

A further explanation of the actual layout of memory is also important. We have talked about rows and columns being accessed, but there is still more to the overall structure. As we had mentioned, rows are also called memory pages, but pages are further grouped into memory banks. Banks of memory can be thought of as something like the set associativity of a cache - each bank can only have one active row at a time. If a second page within a memory bank is requested, the open page must be closed before the new page can be opened. In certain situations, if two different pages within the same bank are requested in rapid succession, additional delays can occur, as a page must remain active for a minimum amount of time. Increasing the number of banks reduces the chance of this happening, so generally speaking, having more banks can help to improve memory performance. There is also a trade off, however, as increasing the number of banks requires additional logic in the memory controller and other components related to the memory subsystem.

Keep this initial explanation of the RAM access pattern in mind when we talk about timings in a moment, but now we need to go back a step and refine our description of how memory is accessed.

Index Refining the Memory Access Description


View All Comments

  • Lynx516 - Tuesday, September 28, 2004 - link

    Your description of how SDRAM works is wrong. you do not bust down the rows as your artcle implys but instead it bursts along the columns.

    The whole column is sent imeadiatly but the other columns in the burst are not and are sent sequencially (idealy not quite the case if you want to interleave them).

    Comparing Banks to set associativity is probably counter productive as most of your reader wont fully under stand how it works. And infact comparing banks to set associativity is a bad annalogy. A better one would be just to say taht the memmory space in the chip is split up into banks.

    On top of this you have referred to a detailed comparsion of DRAM types. Even though there are many different types of DRAM most are not that interesting or used that much in PCs. I also assume that as you have said this you will not be talking about SRAM or RDRAM in forth coming articles which highlight the different approaches that can be taken when designing a memory sub system. (SRAM the low latency, high bandwidth but low density, RDRAM the serial approach)

    I assume you are going to talk abit about how a memory controller works as they are one of the most complex components in a PC (more complex than the exectution core of a CPU) but you have not refered to any plans to talk about memory controller and how the type of memory you are using affects the design of a memory controller.

    All in all a pretty confusingly written article. If you want a DRAM for beginners arstechnica have two good articles (though one is fairly old but atleast correctly and CLEARLY describes how SDRAM works).

  • Resh - Tuesday, September 28, 2004 - link

    I really think that some diagrams would help, especially for novices like #10. Other than that, great article and hope to see the follow-ups soon. Reply
  • Modal - Tuesday, September 28, 2004 - link

    Great article, thanks. I like these "this is how the pieces of your computer work" articles... very interesting stuff, but it's usually written in far too complicated a manner for a relative novice like me. This was quite readable and understandable however; nice work. Reply
  • danidentity - Tuesday, September 28, 2004 - link

    This is one of the best articles I've seen at Anandtech in a long while, keep up the good work. Reply
  • deathwalker - Tuesday, September 28, 2004 - link

    I..for one, would rather have 1 GB of CL 2.5 high quality memory than 512 MB of CL 2 high quality memory. I'm conviced that in this instance quantity wins out over speed. Reply
  • AlphaFox - Tuesday, September 28, 2004 - link

    where are the pictures? ;) Reply
  • Pollock - Tuesday, September 28, 2004 - link

    Excellent read! Reply
  • mino - Tuesday, September 28, 2004 - link

    Sry for triple post but some major typpos:
    "1) buy generic memory until your budget could afford no more than 512M DDR400"
    should be:
    "1) buy generic memory until your budget could afford more than 512M DDR400"
    "Goog"(ROFL) should be "Good"
    onother -> another
    Hope that's all ;)
  • mino - Tuesday, September 28, 2004 - link

    OK, 3 rules ;) - I added 3rd after some thought. Reply
  • mino - Tuesday, September 28, 2004 - link

    #2 You are missing one important point. That is, unless You can(want) afford at least 512M high quality RAM, it makes NO SENSE to buy 256M DDR400 CL2 since there are 2 basic rules:

    1) buy generic memory until your budget could afford no more than 512M DDR400
    2) then spend some aditional money for brand memory
    3) then go 1G and only at this point spent all additional money for better latencies and so on.

    Also do remember that at many shops(here in Slovakia) there is 3 or 4 yrs warranty for generic memory(like A-DATA) and also if you have major problems with compatibility they will usually allow you to choose different brand/type for your board for no additional cost except price difference. Also in case the memory works fine with onother board.
    Also Twinmos parts have 99month warranty (for price 10% higher than generic). That speaks for itself.

    Except this little missing part of reality,

    Goog work Jarred.

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