Deciphering the New Cache Hierarchy

The cache hierarchy is a significant deviation from recent previous AMD designs, and most likely to its advantage.  The L1 data cache is both double in size and increased in associativity compared to Bulldozer, as well as being write-back rather than write-through. It also uses an asymmetric load/store implementation, identifying that loads happen more often than stores in the critical paths of most work flows. The instruction cache is no longer shared between two cores as well as doubling in associativity, which should decrease the proportion of cache misses. AMD states that both the L1-D and L1-I are low latency, with details to come.

The L2 cache sits at half a megabyte per core with 8-way associativity, which is double that of Intel’s Skylake which has 256 KB/core and is only 4-way. On the other hand, Intel’s L3/LLC on their high-end Skylake SKUs is at 2 MB/core or 8 MB/CPU, whereas Zen will feature 1 MB/core and both are at 16-way associativity.

Edit 7:18am: Actually, the slide above is being slightly evasive in its description. It doesn't say how many cores the L3 cache is stretched over, or if there is a common LLC between all cores in the chip. However, we have recieved information from a source (which can't be confirmed via public AMD documents) that states that Zen will feature two sets of 8MB L3 cache between two groups of four cores each, giving 16 MB of L3 total. This would means 2 MB/core, but it also implies that there is no last-level unified cache in silicon across all cores, which Intel has. The reasons behind something like this is typically to do with modularity, and being able to scale a core design from low core counts to high core counts. But it would still leave a Zen core with the same L3 cache per core as Intel.

Cache Levels
  Bulldozer
FX-8150
Zen Broadwell-E
i7-6950X
Skylake
i7-6700K
L1 Instruction 64 KB 2-way
per module
64 KB 4-way 32 KB 8-way 32 KB 8-way
L1 Data 16 KB 4-way
Write Through
32 KB 8-way
Write Back
32 KB 8-way
Write-Back
32 KB 8-way
Write-Back
L2 2 MB 16-way
per module
512 KB 8-way 256 KB 8-way 256 KB 4-way
L3 1 MB/core
64-way
1 or 2 MB/core ?
16-way
2.5 MB/core
16/20-way
2 MB/core
16-way

What this means, between the L2 and the L3, is that AMD is putting more lower level cache nearer the core than Intel, and as it is low level it becomes separate to each core which can potentially improve single thread performance. The downside of bigger and lower (but separate) caches is how each of the cores will perform snoop in each other’s large caches to ensure clean data is being passed around and that old data in L3 is not out-of-date. AMD’s big headline number overall is that Zen will offer up to 5x cache bandwidth to a core over previous designs.

Zen High Level Block Diagram Low Power, FinFET and Clock Gating
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  • BrokenCrayons - Thursday, August 18, 2016 - link

    Hmm...interesting news to say the least, but I'm reluctant to make any assumptions until after Zen is out there being tested. A lot of us were interested in AMD's construction equipment series processors and were disappointed by the final product.
  • Chaser - Thursday, August 18, 2016 - link

    Good on AMD! I am hopeful for them with Zen as many others are.
  • ikjadoon - Thursday, August 18, 2016 - link

    Hmm....nice timing with IDF. Besides the fantasy of getting XPoint in a consumer drive in 5 years, I agree: most people are more interested in AMD. Cautiously (remember the RX 480 presentation?) optimistic.

    At the very least, we'll have some competition around the $300 CPU range. Fairly sure the i7-6700K is priced a little too much higher than the i5-6600K.
  • melgross - Thursday, August 18, 2016 - link

    Most people are more interested in AMD? In what way?
  • nandnandnand - Thursday, August 18, 2016 - link

    AMD's Zen 4/6/8 cores will be a better value than Intel's i7 quad cores. That's what way.
  • Cygni - Thursday, August 18, 2016 - link

    "Will be" sounds pretty definitive considering they aren't even on the market yet and we have no idea how Intel will react with prices or products.

    You would think people would learn not to over hype products that haven't even come out (see: No Man's Sky) but here we are again...
  • StrangerGuy - Thursday, August 18, 2016 - link

    Yeah, and projected products never gets delayed or meets the hype either.
  • Flunk - Thursday, August 18, 2016 - link

    In the competition lowers prices way.
  • ikjadoon - Thursday, August 18, 2016 - link

    In the most basic way possible: reading the news, hehe. I think most people (who aren't interested in X-Point) even realize IDF2016 is happening right now, where Intel showed off Kaby Lake silicon inside a Dell laptop running Overwatch.
  • smilingcrow - Thursday, August 18, 2016 - link

    "The fantasy of getting XPoint in a consumer drive in 5 years."

    Firstly, as a replacement purely for NAND in storage most consumers might find it irrelevant.
    Secondly, it will be available for consumers but at prices that only prosumers might be interested in.
    I think the bigger shift for consumers will be with later products that remove the distinction between memory and storage.

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