One of the main features Intel was promoting at the launch of Haswell was TSX – Transactional Synchronization eXtensions. In our analysis, Johan explains that TSX enables the CPU to process a series of traditionally locked instructions on a dataset in a multithreaded environment without locks, allowing each core to potentially violate each other’s shared data. If the series of instructions is computed without this violation, the code passes through at a quicker rate – if an invalid overwrite happens, the code is aborted and takes the locked route instead. All a developer has to do is link in a TSX library and mark the start and end parts of the code.

News coming from Intel’s briefings in Portland last week boil down to an erratum found with the TSX instructions. Tech Report and David Kanter of Real World Technologies are stating that a software developer outside of Intel discovered the erratum through testing, and subsequently Intel has confirmed its existence. While errata are not new (Intel’s E3-1200 v3 Xeon CPUs already have 140 of them), what is interesting is Intel’s response: to push through new microcode to disable TSX entirely. Normally a microcode update would suggest a workaround, but it would seem that this a fundamental silicon issue that cannot be designed around, or intercepted at an OS or firmware/BIOS level.

Intel has had numerous issues similar to this in the past, such as the FDIV bug, the f00f bug and more recently, the P67 B2 SATA issues. In each case, the bug was resolved by a new silicon stepping, with certain issues (like FDIV) requiring a recall, similar to recent issues in the car industry. This time there are no recalls, the feature just gets disabled via a microcode update.

The main focus of TSX is in server applications rather than consumer systems. It was introduced primarily to aid database management and other tools more akin to a server environment, which is reflected in the fact that enthusiast-level consumer CPUs have it disabled (except Devil’s Canyon). Now it will come across as disabled for everyone, including the workstation and server platforms. Intel is indicating that programmers who are working on TSX enabled code can still develop in the environment as they are committed to the technology in the long run.

Overall, this issue affects all of the Haswell processors currently in the market, the upcoming Haswell-E processors and the early Broadwell-Y processors under the Core M branding, which are currently in production. This issue has been found too late in the day to be introduced to these platforms, although we might imagine that the next stepping all around will have a suitable fix. Intel states that its internal designs have already addressed the issue.

Intel is recommending that Xeon users that require TSX enabled code to improve performance should wait until the release of Haswell-EX. This tells us two things about the state of Haswell: for most of the upcoming LGA2011-3 Haswell CPUs, the launch stepping might be the last, and the Haswell-EX CPUs are still being worked on. That being said, if the Haswell-E/EP stepping at launch is not the last one, Intel might not promote the fact – having the fix for TSX could be a selling point for Broadwell-E/EP down the line.

For those that absolutely need TSX, it is being said that TSX can be re-enabled through the BIOS/firmware menu should the motherboard manufacturer decide to expose it to the user. Reading though Intel’s official errata document, we can confirm this:

We are currently asking Intel what the required set of circumstances are to recreate the issue, but the erratum states ‘a complex set of internal timing conditions and system events … may result in unpredictable system behaviour’. There is no word if this means an unrecoverable system state or memory issue, but any issue would not be in the interests of the buyers of Intel’s CPUs who might need it: banks, server farms, governments and scientific institutions.

At the current time there is no road map for when the fix will be in place, and no public date for the Haswell-EX CPU launch.  It might not make sense for Intel to re-release the desktop Haswell-E/EP CPUs, and in order to distinguish them it might be better to give them all new CPU names.  However the issue should certainly be fixed with Haswell-EX and desktop Broadwell onwards, given that Intel confirms they have addressed the issue internally.

Source: Twitter, Tech Report


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  • andrebrait - Tuesday, August 12, 2014 - link

    It's a good year for Intel. First the the USB 3.0 sleep bug (which persists in Intel's mobile 8-series chipsets), now this.
  • TiGr1982 - Tuesday, August 12, 2014 - link

    No, that sleep bug was already discovered last year (2013).
  • TiGr1982 - Tuesday, August 12, 2014 - link

    And don't forget P67 SATA bug in 2011.
  • Samus - Wednesday, August 13, 2014 - link

    They've been lacking some QA since the X58 chipset and Bloomfield/Lynnfield CPU's , their last really solid products. People who bought into those platforms 5-6 years ago still have competitive systems TODAY. Sure, they lack SATA 6Gbps and USB 3.0, but like the SSD 320 (also from that era) they are virtually flawless.

    Since the 6-series chipset and introduction of Sandy Bridge, there has been an unprecedented surge in errata. Most of it is irrelevant to the general consumer (even P67 wasn't an issue unless using ports other than 0 and 1) but it shows the lapse in quality control at Intel. They're better than this!
  • StevoLincolnite - Wednesday, August 13, 2014 - link

    I would think logically the amount of errata in a processor design would increase as the processors design complexity increases with each new successive release.

    For instance it's going to be far more difficult to debug a design when you have in-excess of 2+ billion transisters than one that has 100 million transisters.
  • Laststop311 - Monday, August 18, 2014 - link

    got a 4 year old i7-980x x58 system and it still kicks major ass. 4.2ghz oc on all 6 cores 24gb triple channel ram. The only reason i want to upgrade to x99 is the lack of sata III and usb 3 both of those features would greatly help me. I could easily wait till skylake-e and x99's successor (x119????) and not feel bad at all tho.
  • nandnandnand - Tuesday, August 12, 2014 - link

    1. Introduce cutting-edge new feature years before widespread adoption.
    2. Flub the implementation in 2+ years of chips.

    Good going, Intel.
  • nicmonson - Tuesday, August 12, 2014 - link

    If it took this long to catch the issue, it sounds like it was not an easy bug to find. You make it sounds like it is easy to be the first one to implement some big new thing. The fact that there has only been one issue so far sounds pretty impressive to me.
  • tipoo - Wednesday, August 13, 2014 - link

    That "only one issue" also required them to disable the whole thing...
  • Devfarce - Tuesday, August 12, 2014 - link

    This is interesting. I bought a base model Fall 2013 rMBP 15" with the 2.0 GHz i7-4750HQ and the processor doesn't have TSX enabled. I was kinda mad about this, I wanted this in hopes that some software may implement it. But I suppose now it's a non-issue.

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