The Tour

While this trip to Centaur wasn't my first visit to Austin, it was the first time I had ever visited VIA's x86 CPU division. VIA acquired Centaur 12 years ago, Glenn Henry has been there since the beginning - back when the company was made up of only 4 people.

Centaur's Glenn Henry in front of a giant dual-core Nano die shot

Glenn took us all on a tour of Centaur. The company itself has 101 employees, a number that grew from 70 at the time of the VIA acquisition. Glen insists that in order to compete in this market with much more powerful competitors (AMD:Centaur::Intel:AMD) his operation has to be lean and efficient. Everyone likes to say that, but Glen actually showed me proof.

When designing a microprocessor you don't just come up with an architecture and hope it works. You do tons of simulation. First you simulate in software. You build up a C model of parts of your architecture or the entire architecture if possible and run it against datasets. This is how you determine things like cache sizes, balance of resources, and model even more fundamental architectural decisions. When you get further along you'll actually simulate the hardware on large FPGAs or other systems with similar functionality. The idea at this point is less about performance validation but just functional validation. The road to manufacturing is expensive (silicon masks cost a lot of money) and time intensive (from tapeout to first silicon is at least 2 months), so you want to figure out as much about your chip's performance and functionality/bugs ahead of time.

Visit any chip company and you'll find a server farm. Dozens if not hundreds of networked PCs all designed to do simulation and validation tests on chip designs. Intel, AMD, NVIDIA, they've all got them. I remember visiting NVIDIA's validation labs and being told that they are limited by the amount of physical power they can get to the lab so each server upgrade has to provide better power efficiency.

Glen took me on a tour of Centaur's simulation lab. To say it was a different experience would be an understatement. While some machines were racked, there were a lot of desktop motherboards running Core i5s and Core i7s running out of cases:

The systems that were in cases were water cooled Core i7s, overclocked to 5GHz. There are two folks at Centaur who build each and every one of these machines, and overclock them. You and I know that overclocking both Nehalem and Sandy Bridge results in much better performance for the same dollar amount, but this is the first time I've seen overclocking used to speed up the simulation of microprocessors.

There are similar efforts made all over Centaur. If something can be built more cheaply than it can be bought, Centaur takes the more affordable route. Even Centaur's ovens used for thermal stress testing use a lot of Centaur-built components in order to reduce their total purchase cost to one fifth of what they would be.

While Centaur didn't have a wafer saw on hand, it can solder and package its own die. This station was used to package a dual-core Nano while a number of journalists watched:

I do wonder about Centaur's future especially as its message of low power operation is now front and center with the current smartphone revolution taking place. In the early days Centaur had to convince users that power was important and that performance was good enough. These days the convincing isn't necessary; it's more about execution, vendor relationships and all of the other pieces of the integrated puzzle. Can VIA and Centaur play a more significant role in the future? The ingredients are there, the question is whether or not VIA is willing to take the risk to give it a try.

VIA's QuadCore
Comments Locked


View All Comments

  • todlerix - Thursday, May 12, 2011 - link

  • vol7ron - Thursday, May 12, 2011 - link

    Anand, nice review. If there is no power gating and TDP is locked, did VIA give any indication as to why they implemented clock-gating and did not just maximize the performance to begin with?

    I suspect it may be to reduce heat or wear-leveling, but it'd be nice to hear their reasoning. Still, even if the clock was maxed, I'm not sure it would generate that much heat, or have any long-term impact on the shelf-life.

  • MrSpadge - Thursday, May 12, 2011 - link

    Here TDP probably means "thermal design power" rather than "typical power draw". It's the maximum a system with such a CPU has to deal with, not what the CPU will typically use.
    And their reasoning is probably very simple: clock gating is easier than power gating.

  • Wesleyrpg - Thursday, May 12, 2011 - link

    would be pretty cool to give VIA another go, but i haven't even seen a board to utilises the Dual Core Nano, yet alone the quad core!

    VIA, please get these out to the public!!!!
  • beginner99 - Thursday, May 12, 2011 - link

    Where are the chips? Nano has been around forever but I have never seen a single product here actually using it. Is it limited to USA? Or Asia?
    I think A dual or quad Nano could be nice for a self-made NAS or HTPC.
  • ppeterka - Thursday, May 12, 2011 - link

    Even though this is not a Nano CPU (AFAIK, but I might be wrong on that), ASRock has two VIA boards, an ITX and a "slightly bigger than ITX but lot more features" microATX one:

    They're also rather cheap, going for less than ~$60 even here in Hungary... They might be good budget x86 media-HTPC projects. Especially the one with a suitable PCIe slot to accept a video card with digital output....
  • DanNeely - Thursday, May 12, 2011 - link

    Search for miniITX, nanoITX, and picoITX boards. You'll find lots of companies selling vias hardware.
  • Spazweasel - Thursday, May 12, 2011 - link

    Embedded computing, data acquisition and industrial control.
  • ProDigit - Friday, May 13, 2011 - link

    very little boards because competition generally is better power wise, or performance wise, or feat wise, or price wise, or all 4 together!
  • Griswold - Thursday, May 12, 2011 - link

    Its kinda bizare seeing these illuminated, windowed and overclocked boxes in a productive environment for designing different CPUs. :0

Log in

Don't have an account? Sign up now