DFI UT P35-T2R: Tweakers Rejoice!
by Rajinder Gill on October 18, 2007 2:00 PM EST- Posted in
- Motherboards
BIOS TRD Phase Adjust
465FSB BIOS Settings
For our 465 FSB Prime stable test, we used the 333/800 strap. We set Performance Level 7, targeted a 465FSB x 8 CPU speed, and ran 4GB of OCZ Flex 9200. The remaining BIOS DRAM Settings were as follows:
Even though we have set Performance Level 7 in the DRAM page, this particular TRD Phase sequence is virtually running a Performance Level of 6 throughout the entire TRD cycle with the exception of a single TRD phase set to 7 (Channel 2 Phase 1) to create the breathing space necessary for the Northbridge to hold steady at 465FSB with 4GB of RAM. When setting a series of phases to ENABLED on both channels, Channel 2 will require an offset as can be seen in the list of settings we used above. If Channel 1 Phase 0, Phase 1 and Channel 2 Phase 0 are set to ENABLED, Channel 2 Phase 1 must be set to AUTO.
Running two or more corresponding phases at ENABLED on both channels is more aggressive, as it sets the corresponding TRD phase registers to -1 at the same point of the TRD cycle, resulting in a lower latency and thus a higher load on the chipset. The general advantage of TRD phase adjustments is to increase FSB margins while retaining significant amounts of latency and bandwidth at FSBs that fall between the borders of two Performance Levels.
Setting a single channel's phase to ENABLED while the corresponding phase for the other channel is set to AUTO results in a very slight gain in latency and bandwidth, which can be useful for maximizing overall performance.
The above timing and phase combinations are only applicable for the setting of 465FSB using the 333/800 divider and Performance Level 7. Scaling the FSB higher will require further tuning and perhaps returning some of the phases back to AUTO. We must consider that various memory settings can affect the level of TRD adjustments that can be made. Experimentation will be required by the user when changing CPU/RAM MHz (FSB) and also primary/secondary RAM timings.
465FSB BIOS Settings
For our 465 FSB Prime stable test, we used the 333/800 strap. We set Performance Level 7, targeted a 465FSB x 8 CPU speed, and ran 4GB of OCZ Flex 9200. The remaining BIOS DRAM Settings were as follows:
| 465FSB BIOS Settings | |
| CPU Feature | |
| Thermal Management Control | Disabled |
| PPM (EIST) Mode | Disabled |
| Limit CPUID MaxVal | Disabled |
| CIE Function | Disabled |
| Execute Disable Bit | Enabled |
| Virtualization Technology | Enabled |
| Core Multi-Processing | Enabled |
| Exist Setup Shutdown | Mode 2 |
| CLOCK VC0 divider | AUTO |
| CPU Clock Ratio | 8x |
| Target CPU Clock | 3722MHz |
| CPU Clock | 465FSB |
| Boot Up Clock | AUTO |
| DRAM Speed | 333MHz/800MHz |
| Target DRAM Speed | DDR2-1116MHz |
| PCIE Clock | 100MHz |
| Voltage Settings | |
| CPU VID Control | 1.4375 |
| CPU VID Special Add | AUTO |
| DRAM Voltage Control | 2.12 |
| SB 1.05V Voltage | 1.07v |
| SB Core/CPU PLL Voltage | 1.55v |
| NB Core Voltage | 1.65 |
| CPU VTT Voltage | 1.60v |
| VCore Droop Control | Disabled |
| Clockgen Voltage Control | 3.45v |
| GTL+ Buffers Strength | Strong |
| Host Slew Rate | Weak |
| GTL REF Voltage Control | Enabled |
| x CPU GTL1/3 REF Volt | 115 |
| x CPU GTL 0/2 REF Volt | 115 |
| x North Bridge GTL REF Volt | 117 |
| DRAM Timing | |
| Enhance Data transmitting | FAST |
| Enhance Addressing | FAST |
| T2 Dispatch | Disabled |
| Channel 1 CLK Crossing Setting | More Aggressive |
| Channel 2 CLK Crossing Setting | More Aggressive |
| CH1CH2 Common CLK Crossing Setting | More Aggressive |
| CAS Latency Time (tCL) | 5 |
| RAS# to CAS# Delay (tRCD) | 5 |
| RAS# Precharge (tRP) | 4 |
| Precharge Delay (tRAS) | 9 |
| All Precharge to Act | 4 |
| REF to ACT Delay (tRFC) | 30 |
| Performance Level | 7 |
| Read delay phase adjust | SEE BELOW |
| MCH ODT Latency | 1 |
| Write to PRE Delay (tWR) | 12 |
| Rank Write to Read (tWTR) | 10 |
| ACT to ACT Delay (tRRD) | 3 |
| Read to Write Delay (tRDWR) | 8 |
| Ranks Write to Write (tWRWR) | AUTO |
| Ranks Read to Read (tRDRD) | AUTO |
| Ranks Write to Read (tWRRD) | AUTO |
| Read CAS# Precharge (tRTP) | 3 |
| ALL PRE to Refresh | 4 |
| PCIE Slot Config | 1X 1X |
| CPU Spread Spectrum | Disabled |
| PCIE Spread Spectrum | Disabled |
| SATA Spread Spectrum | Disabled |
| TRD Phase adjust settings | |
| Channel 1 Phase 0 Pull-In | ENABLED (TRD 6) |
| Channel 1 Phase 1 Pull-In | ENABLED (TRD 6) |
| Channel 1 Phase 2 Pull-In | ENABLED (TRD 6) |
| Channel 1 Phase 3 Pull-In | ENABLED (TRD 6) |
| Channel 1 Phase 4 Pull-In | ENABLED (TRD 6) |
| Channel 2 Phase 0 Pull-In | ENABLED (TRD 6) |
| Channel 2 Phase 1 Pull-In | AUTO (TRD 7) |
| Channel 2 Phase 2 Pull-In | ENABLED (TRD 6) |
| Channel 2 Phase 3 Pull-In | ENABLED (TRD 6) |
| Channel 2 Phase 4 Pull-In | ENABLED (TRD 6) |
Even though we have set Performance Level 7 in the DRAM page, this particular TRD Phase sequence is virtually running a Performance Level of 6 throughout the entire TRD cycle with the exception of a single TRD phase set to 7 (Channel 2 Phase 1) to create the breathing space necessary for the Northbridge to hold steady at 465FSB with 4GB of RAM. When setting a series of phases to ENABLED on both channels, Channel 2 will require an offset as can be seen in the list of settings we used above. If Channel 1 Phase 0, Phase 1 and Channel 2 Phase 0 are set to ENABLED, Channel 2 Phase 1 must be set to AUTO.
Running two or more corresponding phases at ENABLED on both channels is more aggressive, as it sets the corresponding TRD phase registers to -1 at the same point of the TRD cycle, resulting in a lower latency and thus a higher load on the chipset. The general advantage of TRD phase adjustments is to increase FSB margins while retaining significant amounts of latency and bandwidth at FSBs that fall between the borders of two Performance Levels.
Setting a single channel's phase to ENABLED while the corresponding phase for the other channel is set to AUTO results in a very slight gain in latency and bandwidth, which can be useful for maximizing overall performance.
The above timing and phase combinations are only applicable for the setting of 465FSB using the 333/800 divider and Performance Level 7. Scaling the FSB higher will require further tuning and perhaps returning some of the phases back to AUTO. We must consider that various memory settings can affect the level of TRD adjustments that can be made. Experimentation will be required by the user when changing CPU/RAM MHz (FSB) and also primary/secondary RAM timings.
Facebook
Twitter
RSS
30 Comments
View All Comments
Rocket321 - Tuesday, October 23, 2007 - link
I would like to see the overclocking results put into a graph or chart of some kind.I guess tweakers might like the screenshots as "proof" that the overclock ran, but personally I trust you and would rather just have one place to look rather than clicking to enlarge multiple screenshots sequentially.
It was a great review though, I look forward to the future tweaker guides & reviews.
Raja Gill - Wednesday, October 24, 2007 - link
There will be a more typical Anandtech look to future articles, with the DFI board revisited for a round up on a suite of benchmarks, this will be used to cross compare with other boards, clocked to equivalent with board maximums in the range and voltage. In terms of the screenshots, it is nice to have 1 persons trust, but there are many we have to please and not everyone is always as convinced..thanks for the suggestions..
Next up is the Asus Maximus Formula..
regards
Raja
Jodiuh - Thursday, October 25, 2007 - link
Specifically Windvd conversions from divx/xvid to DVD would be wonderful as I've found this app benefits from a solid OC.beoba - Friday, October 19, 2007 - link
It'd be great if this came with a glossary."Strap"?
retrospooty - Saturday, October 20, 2007 - link
strap is a term used for memory clocking. for example, at 266mhz bus, memory can be "strapped" to one of the following.266x(stap2)=533 or DDR 1066
266x(strap1.5)=400 or DDR 800
266x(strap1.25)=333 or DDR 666
If you are running at stock 266 there is no way to have DDR 950 because it has to be strapped to one of the above settings.
I use the 1/1 strap so my bus speed is 500x(strap1)=500 or DDR 1000, in most cases 1/1 is the most efficient, if you can utilize it with your particular hardware, do it.
Avalon - Thursday, October 18, 2007 - link
Unfortunately, DFI's asking price of admission continues to rise for each new board they release. I was mildly annoyed when they started selling boards for $200+ that had little to no tangible benefit over $100-$150 boards, but now they're at the $300 mark? No thanks.This board is for someone who likes to spend his time tweaking and not actually using his computer.
retrospooty - Saturday, October 20, 2007 - link
"This board is for someone who likes to spend his time tweaking and not actually using his computer."The article title is called "Tweakers Rejoice" after all. The idea is not to tweak forever . I did spend alot of time over the first few weeks, but now that its tweaked, I just use it as is.
Avalon - Sunday, October 21, 2007 - link
Yes, I am quite capable of reading the article title. My whole point is that you are working for diminishing returns that I feel could be better spent using your system. If you're doing it to set a record, fantastic. I support that.retrospooty - Sunday, October 21, 2007 - link
Understood... This is obviously not the motherboard for you. I personally love the BIOS options and CMOS reloaded functionality. That alone makes the extra cost well worth it to me. Asus BIOS just sucks, and I have had too many quality problems with them in the past, and Gigabyte just underperforms. I like to know I will not be held back by my motherboard for the next couple of CPU's I buy (will likely get a dual core Penryn on release for under $200, then a high end quad core Penryn a year or so later when it is under $200).I do see your point, but in spite of this article's stock speed comparison (totally pointless for a OC geared mobo), and similar results with one particular CPU, that looks as if it has an FSB limit equal on all 3 boards (meaning the CPU is holding it back) This board overclocks and performs better than any ASUS, or Gigabyte, or any other board out there. If AT tested the max FSB limits on a dozen or so CPU's, or if they had a "golden sample" that had a high FSB limit, you would see the difference. Also if they had time to test many diff RAM stocks and to tweak the memory settings you would also see the difference. Its a good article, but no reviewer has time to really dig into this mobo and all it has to offer. I do feel the article did a good job at explaining that.
JNo - Sunday, October 21, 2007 - link
"I like to know I will not be held back by my motherboard for the next couple of CPU's I buy"I don't know much about overclocking and I hold your views valid Retrospooty but surely this is still a lot of money that will still be needed to replaced in the short/medium-term if a) you want to start using DDR3 once prices come down b) if GPUs come out that take advantage of PCI-E 2 standard (as used on X38). So all that money is only paying for great OC'ing potential for *now* only... no?