Xeon E7 v3 SKUs and prices

Intel SKU list has always been complex and very long.  For reference, this is what the Xeon E7 v2 line-up looked like when it launched in 2014:

There is a scalable 2S line that is not scalable beyond 2 sockets, a frequency optimized 8857 which is probably faster in many applications than the 8893 and so on.

Luckily, with the introduction of the Xeon E7 v3, Intel simplified the SKU list. 

First of all, the hardly scalable 2 socket version is gone. And at the low-end, you now get a 8-core processor at 2 GHz instead of a 6-core at 1.9 GHz. Well done, Intel.

The high-end models are all capable of running in 8 socket configurations. But the enterprise people looking for a high-end quad socket system have to pay a bit more: about 8 to 10%.  Most enterprise people will not care, but getting 20% more cores (slightly improved) at 8-10% lower clocks while paying about 8% more is not exactly a vast improvement. Of course these are paper specs, but Intel used to be (a lot) more generous. 

Intel's own slides confirm this. The gains in SPECint2006_rate are pretty small to justify the price increase. Intel claims higher OLTP (TPC-C) increases, but the mentioned gains are rather optimistic. For example, the HammerDB benchmark runs 29% faster on the E7-8890 v3 than on the E7-4890v2. This benchmark is much more transparant, straight forward and easier to reproduce than TPC-C, so we feel it is probably closer to the real world. Secondly, in both cases (HammerDB and TPC-C), the E7-8890v3 had twice as much memory (1 TB vs 512 GB) memory as its predecessor. 

Lastly, these are benchmarks after all. In the real world systems are not running at full speed, so the gains are much smaller.  So it seems that in most applications besides the TSX/AVX2 enabled ones, the gains will be rather small. 

Haswell Architecture Improvements: TSX & More The Competitor: IBM's POWER8
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  • PowerTrumps - Saturday, May 9, 2015 - link

    I'm sure the author will update the article unless this was a Intel cheerleading piece.
  • name99 - Friday, May 8, 2015 - link

    The thing is called E7-8890. Not E7-5890?
    WTF Intel? Is your marketing team populated by utter idiots? Exactly what value is there in not following the same damn numbering scheme that your product line has followed for the past eight years or so?

    Something like that makes the chip look like there's a whole lot of "but this one goes up to 11" thinking going on at Intel...
  • name99 - Friday, May 8, 2015 - link

    OK, I get it. The first number indicates the number of glueless chips, not the micro-architecture generation. Instead we do that (apparently) with a v2 or v3 suffix.
    I still claim this is totally idiotic. Far more sensible would be to use the same scheme as the other Intel processors, and use a suffix like S2, S4, S8 to show the glueless SMP capabilities.
  • ZeDestructor - Friday, May 8, 2015 - link

    They've been using this convention since Westmere-EX actually, at which point they ditched their old convention of a prefix letter for power tier, followed by one digit for performance/scalability tier, followed by another digit for generation then the rest for individual models. Now we have 2xxx for dual socket, 4xxx for quad socket and 8xxx for 8+ sockets, and E3/E5/E7 for the scalability tier. I'm fine with either, though I have a slight preference for the current naming scheme because the generation is no longer mixed into the main model number.
  • Morawka - Saturday, May 9, 2015 - link

    man the power 8 is a beefy cpu... all that cache, you'd think it would walk all over intel.. but intel's superior cpu design wins
  • PowerTrumps - Saturday, May 9, 2015 - link

    please explain
  • tsk2k - Saturday, May 9, 2015 - link

    Where are the gaming benchmarks?
  • JohanAnandtech - Saturday, May 9, 2015 - link

    Is there still a game with software rendering? :-)
  • Gigaplex - Sunday, May 10, 2015 - link

    Llvmpipe on Linux gives a capable (feature wise) OpenGL implementation on the CPU.
  • Klimax - Saturday, May 9, 2015 - link

    Don't see POWER getting anywhere with that kind of TDP. There will be dearth of datacenters and other hosting locations retooling for such thing. And I suspect not many will even then take it as cooling and power costs will be damn too high.

    Problem is, IBM can't go lower with TDP as architecture features enabling such performance are directly responsible for such TDP. (Just L1 consumes 2W to keep few cycles latency at high frequency)

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