The fourth and final of the major SC15 conference announcements/briefings for today comes Intel. As Intel is in the middle of executing on their previously announced roadmap, they aren’t at SC15 with any announcements of new products this year. However after almost two years of build-up since its initial announcement, Intel’s second-generation Xeon Phi, Knights Landing, is finally gearing up for its full launch.

The 14nm successor to Knights Corner (1st gen Xeon Phi), Knights Landing implements AVX-512, Multi-Channel DRAM (MCDRAM), and a new CPU core based on Intel’s Silvermont architecture. Knights Landing is now shipping to Intel’s first customers and developers as part of their early ship program, and pre-production systems for demonstrating supercomputer designs are up and running. Knights Landing is ultimately ramping up for general availability in Q1 of 2016, at which point I expect we’ll also get the final SKU specifications from Intel.

Meanwhile Knights Landing’s partner in processing, Intel’s Omni-Path Architecture, is formally launching at SC15. Intel’s own take on a high bandwidth low-latency interconnect for HPC, Omni-Path marks Intel’s greatest efforts yet to diverge from InfiniBand and go their own way in the market for interconnect fabrics. We covered Omni-Path a bit earlier this year at Intel’s IDF15 conference, so there aren’t any new technical details to touch upon, however Intel is now throwing out their official performance figures for Omni-Path versus InfiniBand EDR, including the power savings of their larger 48-port switch capabilities.

Ultimately Knights Landing and Omni-Patch Architecture are part of Intel’s larger efforts to build a whole ecosystem, which they’ve been calling the System Scalable Framework. Along with the aforementioned hardware, Intel will be showing off some of the latest software developments for the SSF on the SC15 show floor this week.

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  • Kevin G - Monday, November 16, 2015 - link

    Huh, it appears that Intel could make their press deck a bit more clear. The one regarding the Xeon Phi mentions 'high bandwidth memory'. At first glance I thought that was referring to the same HBM technology on the Fury X but all the specs indicate that it actually uses HMC, a similar competitor. Of course the reality is that Intel is using high bandwidth memory generically here but it is confusing. Reply
  • patrickjp93 - Monday, November 16, 2015 - link

    It doesn't help HMC was actually the first "high-bandwidth memory" designed and was deployed back in 2013 for the Oracle Sparc Fujitsu systems. Reply
  • testbug00 - Monday, November 16, 2015 - link

    Because HBM means high bandwidth memory. It's not a specific definition last I checked. WideIO, HMC, and die stacking RAM over a wide bus are all types of HBM. Just someone(s) decided naming one HBM was smart. For some weird reason. Reply
  • BurntMyBacon - Wednesday, November 18, 2015 - link

    @testbug00: "Just someone(s) decided naming one HBM was smart. For some weird reason."

    Free publicity. Every time someone decides to refer to one of these technologies generically, people think of HBM (the GPU specific implementation). People post questions in forums. Others post answers to straighten out misunderstands. Some even make post about the potential merits of HBM that isn't even in use in the topic of discussion. Then lots of others read the post. Finally, someone makes a post about how all this works to bring publicity to the technology. That's just the forum post version of getting publicity.
    Reply
  • extide - Monday, November 16, 2015 - link

    I believe it is more closely related to the Micron HMC than the Hynix HBM on the Fury. Reply
  • nikaldro - Monday, November 16, 2015 - link

    HMC isn't really a competitor to HBM. They're meant to bite completely different markets. Reply
  • aaa123 - Friday, November 20, 2015 - link

    what a crap. intel really sucks. mellanox and nvidia are at least
    3 years in front of them. the landing
    is around 20% behind latest nv on
    single prec.
    Reply

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