The Architecture

We'll start, logically, at the front end of a Bulldozer module. The fetch and decode logic in each module is shared by both integer cores. The role this logic plays is to fetch the next instruction in the thread being executed, decode the x86 instruction into AMD's own internal format, and pass the decoded instruction onto the scheduling hardware for execution.

AMD widened the K8 front end with Bulldozer. Each module is now able to fetch and decode up to four x86 instructions from a single thread in parallel. Each of the four decoders are equally capable. Remembering that each Bulldozer module appears as two cores, the front end can only pick 4 instructions to fetch and decode from a single thread at a time. A single Bulldozer module can switch between threads as often as every clock.

Decode hardware isn't very expensive on its own, but duplicating it four times across multiple cores quickly adds up. Although decode width has increased for a single core, multi-core Bulldozer configurations can actually be at a disadvantage compared to previous AMD architectures. Let's look at the table below to understand why:

Front End Comparison
  AMD Phenom II AMD FX Intel Core i7
Instruction Decode Width 3-wide 4-wide 4-wide
Single Core Peak Decode Rate 3 instructions 4 instructions 4 instructions
Dual Core Peak Decode Rate 6 instructions 4 instructions 8 instructions
Quad Core Peak Decode Rate 12 instructions 8 instructions 16 instructions
Six/Eight Core Peak Decode Rate 18 instructions (6C) 16 instructions 24 instructions (6C)

For a single instruction thread, Bulldozer offers more front end bandwidth than its predecessor. The front end is wider and just as capable so this makes sense. But note what happens when we scale up core count.

Since fetch and decode hardware is shared per module, and AMD counts each module as two cores, given an equivalent number of cores the old Phenom II actually offers a higher peak instruction fetch/decode rate than the FX. The theory is obviously that the situations where you're fetch/decode bound are infrequent enough to justify the sharing of hardware. AMD is correct for the most part. Many instructions can take multiple cycles to decode, and by switching between threads each cycle the pipelined front end hardware can be more efficiently utilized. It's only in unusually bursty situations where the front end can become a limit.

Compared to Intel's Core architecture however, AMD is at a disadvantage here. In the high-end offerings where Intel enables Hyper Threading, AMD has zero advantage as Intel can weave in instructions from two threads every clock. It's compared to the non-HT enabled Core CPUs that the advantage isn't so clear. Intel maintains a higher instantaneous decode bandwidth per clock, however overall decoder utilization could go down as a result of only being able to fill each fetch queue from a single thread.

After the decoders AMD enables certain operations to be fused together and treated as a single operation down the rest of the pipeline. This is similar to what Intel calls micro-ops fusion, a technology first introduced in its Banias CPU in 2003. Compare + branch, test + branch and some other operations can be fused together after decode in Bulldozer—effectively widening the execution back end of the CPU. This wasn't previously possible in Phenom II and obviously helps increase IPC.

A Decoupled Branch Predictor

AMD didn't disclose too much about the configuration of the branch predictor hardware in Bulldozer, but it is quick to point out one significant improvement: the branch predictor is now significantly decoupled from the processor's front end.

The role of the branch predictor is to intercept branch instructions and predict their target address, rather than allowing for tons of cycles to go by until the branch target is known for sure. Branches are predicted based on historical data. The more data you have, and the better your branch predictors are tuned to your workload, the more accurate your predictions can be. Accurate branch prediction is particularly important in architectures with deep pipelines as a mispredict causes more instructions to be flushed out of the pipe. Bulldozer introduces a significantly deeper pipeline than its predecessor (more on this later), and thus branch prediction improvements are necessary.

In both Phenom II and Bulldozer, branches are predicted in the front end of the pipe alongside the fetch hardware. In Phenom II however, any stall in the fetch pipeline (e.g. fetching an instruction that wasn't in cache) would stop the whole pipeline including future branch predictions. Bulldozer decouples the branch prediction hardware from the fetch pipeline by way of a prediction queue. If there's a stall in the fetch pipeline, Bulldozer's branch prediction hardware is allowed to run ahead and continue making future predictions until the prediction queue is full.

We'll get to the effectiveness of this approach shortly.

Scheduling and Execution Improvements

As with Sandy Bridge, AMD migrated to a physical register file architecture with Bulldozer. Data is now only stored in one location (the physical register file) and is tracked via pointers back to the PRF as operations make their way through the execution engine. This is a move to save power as copying data around a chip is hardly power efficient.

The buffers and queues that feed into the execution engines of the chip are all larger on Bulldozer than they were on Phenom II. Larger data structures allows for better instruction level parallelism when trying to execute operations out of order. In other words, the issue hardware in Bulldozer is beefier than its predecessor.

Unfortunately where AMD took one step forward in issue hardware, it does a bit of a shuffle when it comes to execution resources themselves. Let's start with the positive: Bulldozer's integer execution cores.

Integer Execution

Each Bulldozer module features two fully independent integer cores. Each core has its own integer scheduler, register file and 16KB L1 data cache. The integer schedulers are both larger than their counterparts in the Phenom II.

The biggest change here is each integer core now has two ports instead of three. A single integer core features two AGU/ALU ports, compared to three in the previous design. AMD claims the third ALU/AGU pair went mostly unused in Phenom II, and as a result it's been removed from Bulldozer.

With larger structures feeding into the integer cores, AMD should be able to have an easier time of making use of the integer units than in previous designs. AMD could, in theory, execute more integer operations per core in Phenom II however AMD claims the architecture was typically bound elsewhere.

The Shared FP Core

A single Bulldozer module has a single shared FP core for use by up to two threads. If there's only a single FP thread available, it is given full access to the FP execution hardware, otherwise the resources are shared between the two threads.

Compared to a quad-core Phenom II, AMD's eight-core (quad-module) FX sees no drop in floating point execution resources. AMD's architecture has always had independent scheduling for integer and floating point instructions, and we see the same number of execution ports between Phenom II cores and FX modules. Just as is the case with the integer cores, the shared FP core in a Bulldozer module has larger scheduling hardware in front of it than the FPU in Phenom II.

The problem is AMD had to increase the functionality of its FPU with the move to Bulldozer. The Phenom II architecture lacks SSE4 and AVX support, both of which were added in Bulldozer. Furthermore, AMD chose Bulldozer as the architecture to include support for fused multiply-add instructions (FMA). Enabling FMA support also increases the relative die area of the FPU. So while the throughput of Bulldozer's FPU hasn't increased over K8, its capabilities have. Unfortunately this means that peak FP throughput running x87/SSE2/3 workloads remains unchanged compared to the previous generation. Bulldozer will only be faster if newer SSE, AVX or FMA instructions are used, or if its clock speed is significantly higher than Phenom II.

Looking at our Cinebench 11.5 multithreaded workload we see the perfect example of this performance shuffle:

Cinebench 11.5—Multi-Threaded

Despite a 9% higher base clock speed (more if you include turbo core), a 3.6GHz 8-core Bulldozer is only able to outperform a 3.3GHz 6-core Phenom II by less than 2%. Heavily threaded floating point workloads may not see huge gains on Bulldozer compared to their 6-core predecessors.

There's another issue. Bulldozer, at least at launch, won't have to simply outperform its quad-core predecessor. It will need to do better than a six-core Phenom II. In this comparison unfortunately, the Phenom II has the definite throughput advantage. The Phenom II X6 can execute 50% more SSE2/3 and x87 FP instructions than a Bulldozer based FX.

Since the release of the Phenom II X6, AMD's major advantage has been in heavily threaded workloads—particularly floating point workloads thanks to the sheer number of resources available per chip. Bulldozer actually takes a step back in this regard and as a result, you will see some of those same workloads perform worse, if not the same as the outgoing Phenom II X6.

Compared to Sandy Bridge, Bulldozer only has two advantages in FP performance: FMA support and higher 128-bit AVX throughput. There's very little code available today that uses AMD's FMA instruction, while the 128-bit AVX advantage is tangible.

Cache Hierarchy and Memory Subsystem

Each integer core features its own dedicated L1 data cache. The shared FP core sends loads/stores through either of the integer cores, similar to how it works in Phenom II although there are two integer cores to deal with now instead of just one. Bulldozer enables fully out-of-order loads and stores, an improvement over Phenom II putting it on parity with current Intel architectures. The L1 instruction cache is shared by the entire bulldozer module, as is the L2 cache.

The instruction cache is a large 64KB 2-way set associative cache, similar in size to the Phenom II's L1 cache but obviously shared by more "cores". A four-core Phenom II would have 256KB of total L1 I-Cache, while a four core Bulldozer will have half of that. The L1 data caches are also significantly smaller than Bulldozer's predecessor. While Phenom II offered a 64KB L1 D-Cache per core, Bulldozer only offers 16KB per integer core.

The L2 cache is much larger than what we saw in multi-core Phenom II designs however. Each Bulldozer module has a private 2MB L2 cache.

There's a single 8MB L3 cache that's shared among all Bulldozer modules on a chip. In its first incarnation, AMD has no plans to offer a desktop part without an L3 cache. However AMD indicated that the L3 cache was only really useful in server workloads and we might expect future Bulldozer derivatives (ahem, Trinity?) to forgo the L3 cache entirely as a result.

Cache accesses require more clocks in Bulldozer, due to a combination of size and AMD's desire to make Bulldozer a very high clock speed part...

Introduction The Pursuit of Clock Speed
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  • B3an - Wednesday, October 12, 2011 - link

    Yep this really is extremely disappointing. I'm actually going to call this AMD's Pentium 4. Thats how bad this is.

    2 billion transistors - thats a massive increase over the Phenom II X6 and what do we get? Nothing. The Phenom II is atleast as good with WAY less transistors and lower power consumption under load. I'm pretty shocked at how bad Bulldozer is. I wasn't expecting performance clock for clock to be as good as Nehalem, let alone Sandy Bridge, but this is just... appalling. When Ivy Bridge is out the performance difference is going to be MASSIVE.

    Intel are surely going to implement more restrictions and hold there clocks speeds back even further. Theres just no competition anymore. Sad day for consumers.
    Reply
  • bennyg - Wednesday, October 12, 2011 - link

    AMD's Prescott to be exact... ironically that's one thing they seemed to shoot for in deepening pipeline and hoping that process would be better... hopefully this is just immature and soon there will be a GF110-style refresh that does it properly...

    Otherwise the whole next gen of AMD CPUs will continue to fight for scraps at the bottom of the heap... and their laptop CPUs will not even succeed there.
    Reply
  • TekDemon - Wednesday, October 12, 2011 - link

    I don't even know if it's just the process since those power consumption figures seem to suggest that they're being limited by the sheer amount of power it's using and the heat being generated from that. Intel had planned to take the P4 to 10Ghz but the fact that it was a power hog prevented that from realistically happening and it seems like you have the same issue here. The clockspeed potential is clearly there since it can hit 7Ghz under liquid nitrogen but for a normal air heatsink setup this is a recipe for failure. It's just way too power hungry and not fast enough to justify it. Why would anybody choose to use an extra 100 watts for largely the same or worse performance vs an i5 2500K? Reply
  • Thermalzeal - Wednesday, October 12, 2011 - link

    I agree, 2 billion transistors are doing what exactly?

    The worst thing is that the water cooler isn't included with the FX-8150. At the performance levels they are providing, they should have just upped the price 30-50 bucks and provided the cooler gratis. Who's gonna need an AMD branded cooler if their not going to buy bulldozer?

    The other point of these review is that there is no availability of any of the parts. So what a wonderful paper launch we have here. Seems like AMD isn't betting on anyone being interested enough to buy one of these things.

    Blasphemy.
    Reply
  • eanazag - Wednesday, October 12, 2011 - link

    You can find them on Newegg today. The price is jacked up though. Newegg must not read AT. Reply
  • jleach1 - Friday, October 21, 2011 - link

    Sigh...it's quite sad. There must be actual people buying these...either that or the supply is terrible. Because there's no way in hell i'd pay those prices for an AMD processor. Reply
  • defacer - Wednesday, October 12, 2011 - link

    Like most people here, I 'm disappointed with BD performance -- even though I have never owned an AMD CPU after my 386DX/40 myself, competition in the performance segment would be nice for a change.

    I won't argue against "it's not 8 core", but calling it a 4-core is IMHO just as inappropriate (if not more).
    Reply
  • yankeeDDL - Wednesday, October 12, 2011 - link

    Ok, how about 4 modules, with 8 integer EU, 4 fetch, 4 decode, 4 L2 caches ...
    Point being, they are 4 modules, not 8 cores, and from many aspects, they are more similar to a 4-core CPU than to an 8-core CPU, being neither one (somewhere in between).

    The fact of the matter remains: the IPC is bad. In multi-threaded, Integer-intensive tasks, BD should crunch the PhenomII X6 (2 more cores, higher clock speed), but it seems you can hardly see the difference. (ref: Excel 2007 SP! MonteCarlo sims).

    AMD now is left with Llano as the only compelling reason to buy AMD over Intel (for netbooks and small notebooks, where Atom is the contender).
    Against Core, either the FX-8150 goes down to $200 or less, or the i5-2500 is just a better buy for the money.
    The advantage is I don't need a new MoBo (huge advantage for me, but not very compelling, in general).
    Reply
  • yankeeDDL - Wednesday, October 12, 2011 - link

    Forgot to mention, regarding the integer-intensive test: the core-i5 is slower by about 9% slower with 9% slower clock, but only 4 execution units (8 logical, with hyperthreading, but hyperthreading should be nearly irrelevant in this test).
    What a blow.
    Reply
  • Ratman6161 - Wednesday, October 12, 2011 - link

    We can argue about weather its really a 4 core or an 8 core, and the argument is interesting from a technical standpoint. But the proof is in the real world benchmarks. From a practical standpoint, if the benchmarks are not there (and they aren't) then the rest really doesn't matter.

    I looked on Microcenter where you can get a 2600K for $279 and a 2500K for $179. An i5-2400 is only $149. So AMD is going to be right back to having to cut prices and have its top end CPU go up against $149 - $179 Intel parts. Worse yet, it will, at least initially, be competing against its own previous generation parts.

    There is one point of interest though and that is the fact that all the FX's are unlocked (according to the story). So it's pretty likely that an FX 8100 will probably overclock about as high as an 8150 once the process is mature. But there again, among overclockers, AMD could find its highest end 8150 competing against its own lower priced 8100.

    Back in the day, I loved my Athlon 64's and 64 x2's and even though I have switched to an Intel Q6600 and then a 2600K, I still really want AMD to succeed...but its not looking good.
    Reply

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