Sizing Up Servers: Intel's Skylake-SP Xeon versus AMD's EPYC 7000 - The Server CPU Battle of the Decade?
by Johan De Gelas & Ian Cutress on July 11, 2017 12:15 PM EST- Posted in
- CPUs
- AMD
- Intel
- Xeon
- Enterprise
- Skylake
- Zen
- Naples
- Skylake-SP
- EPYC
Memory Subsystem: Latency
The performance of modern CPUs depends heavily on the cache subsystem. And some applications depend heavily on the DRAM subsystem too. We used LMBench in an effort to try to measure cache and memory latency. The numbers we looked at were "Random load latency stride=16 Bytes".
| Mem Hierarchy |
AMD EPYC 7601 DDR4-2400 |
Intel Skylake-SP DDR4-2666 |
Intel Broadwell Xeon E5-2699v4 DDR4-2400 |
| L1 Cache cycles | 4 | 4 | 4 |
| L2 Cache cycles | 12 | 14-22 | 12-15 |
| L3 Cache 4-8 MB - cycles | 34-47 | 54-56 | 38-51 |
| 16-32 MB - ns | 89-95 ns | 25-27 ns (+/- 55 cycles?) |
27-42 ns (+/- 47 cycles) |
| Memory 384-512 MB - ns | 96-98 ns | 89-91 ns | 95 ns |
Previously, Ian has described the AMD Infinity Fabric that stitches the two CCXes together in one die and interconnects the 4 different "Zeppelin" dies in one MCM. The choice of using two CCXes in a single die is certainly not optimal for Naples. The local "inside the CCX" 8 MB L3-cache is accessed with very little latency. But once the core needs to access another L3-cache chunk – even on the same die – unloaded latency is pretty bad: it's only slightly better than the DRAM access latency. Accessing DRAM is on all modern CPUs a naturally high latency operation: signals have to travel from the memory controller over the memory bus, and the internal memory matrix of DDR4-2666 DRAM is only running at 333 MHz (hence the very high CAS latencies of DDR4). So it is surprising that accessing SRAM over an on-chip fabric requires so many cycles.
What does this mean to the end user? The 64 MB L3 on the spec sheet does not really exist. In fact even the 16 MB L3 on a single Zeppelin die consists of two 8 MB L3-caches. There is no cache that truly functions as single, unified L3-cache on the MCM; instead there are eight separate 8 MB L3-caches.
That will work out fine for applications that have a footprint that fits within a single 8 MB L3 slice, like virtual machines (JVM, Hypervisors based ones) and HPC/Big Data applications that work on separate chunks of data in parallel (for example, the "map" phase of "map/reduce"). However this kind of setup will definitely hurt the performance of applications that need "central" access to one big data pool, such as database applications and big data applications in the "Shuffle phase".
Memory Subsystem: TinyMemBench
To double check our latency measurements and get a deeper understanding of the respective architectures, we also use the open source TinyMemBench benchmark. The source was compiled for x86 with GCC 5.4 and the optimization level was set to "-O3". The measurement is described well by the manual of TinyMemBench:
Average time is measured for random memory accesses in the buffers of different sizes. The larger the buffer, the more significant the relative contributions of TLB, L1/L2 cache misses, and DRAM accesses become. All the numbers represent extra time, which needs to be added to L1 cache latency (4 cycles).
We tested with dual random read, as we wanted to see how the memory system coped with multiple read requests.
L3-cache sizes have increased steadily over the years. The Xeon E5 v1 had up to 20 MB, v3 came with 45 MB, and v4 "Broadwell EP" further increased this to 55 MB. But the fatter the cache, the higher the latency became. L3 latency doubled from Sandy Bridge-EP to Broadwell-EP. So it is no wonder that Skylake went for a larger L2-cache and a smaller but faster L3. The L2-cache offers 4 times lower latency at 512 KB.
AMD's unloaded latency is very competitive under 8 MB, and is a vast improvement over previous AMD server CPUs. Unfortunately, accessing more 8 MB incurs worse latency than a Broadwell core accessing DRAM. Due to the slow L3-cache access, AMD's DRAM access is also the slowest. The importance of unloaded DRAM latency should of course not be exaggerated: in most applications most of the loads are done in the caches. Still, it is bad news for applications with pointer chasing or other latency-sensitive operations.
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sharath.naik - Wednesday, July 12, 2017 - link
http://www.anandtech.com/show/10158/the-intel-xeon...Here is the link for you a single Xeon E5 v4 22 core does 5.3 (Dual at 5.9)jobs a day compared to dual Epyc 6.3. Ok they are 7% apart for dual socket but only 15% faster for dual epyc compared to single Xeon E5. Big Data does not do well in NUMA set up, same is the case with any regular large data applications. Try running EPYC without splitting spark into multiple processes, you will see how terrible a dual EPYC is going to be (the review mentions it but does not give a graph). Now this is terrible, to use EPYC first you need to change the way you build and run the applications and then expect 7-15% advantage vs a 2000$ CPU. It simple shows that EPYC is only use full for VMs and some synthetic tests. Any applications that deal with data can and should stay away from EPYC
warreo - Friday, July 14, 2017 - link
Why are you comparing Spark 1.5 benchmarks against 2.1.1? Johan pointed out in the article why they are not comparable and why he is using the new 2.1.1 benchmark.The exact Dual Xeon E5 2699 v4 you are referencing that did 5.9 jobs per day in Spark 1.5 only does 4.9 jobs per day on Spark 2.1.1. If we assume a similar % gap between dual and single as it was in Spark 1.5, then a single Xeon E5 2699 v4 would be capable of only 4.4 jobs per day in Spark 2.1.1, which is a 43% difference compared to dual Epycs.
Even leaving that aside, your exact arguments can be applied to the new Xeons as well, which are only 5% faster than the Epycs. Do you think the new Xeons suck as well?
Same thing for splitting Spark into multiple processes and needing to re-write applications -- you also run into the exact same issue with the new Xeons (which Johan also explictly points out).
Based on your arguments, I'm confused why you are taking aim only at Epyc and not the new Xeons. Please let me know if I'm missing something here.
AleXopf - Wednesday, July 12, 2017 - link
Username checks outdeltaFx2 - Wednesday, July 12, 2017 - link
"four 8core desktop dies" Oh, on the contrary. It's really a 4 die MCM server part, and each die is being sold as a desktop part. Nobody puts interconnect (fabric) on a desktop part. MCM is something intel has also done way back in the dual core era, and IBM continues to do. Don't float that canard re. desktop parts, it's just a design choice. AMD isn't trying to beat Intel in every market, just in some, and it does that. It might not win in HPC or big enterprise database (idk), but if you are a public cloud provider in the business of renting 4c8t or 8c16t VMs, AMD has a solid product. Now throw in the 128 PCIe lanes, which intel can't come close to. In fact, a 32c Naples in 1P is something that Intel has nothing to compete against for applications like storage, GPGPU, etc. The question isn't if it's good enough to run Intel out of business in the server space; that's not happening. It didn't when AMD had a superior product in Opteron. The question is, is it good enough for 5-10% market share in 2018-2019?"Intel cores are superior than AMD so a 28 core xeon is equal to ~40 cores if you compare again Ryzen core so this whole 28core vs 32core is a marketing trick". And yet all the numbers presented above point to the opposite. Ryzen != Epyc and i7700K != Syklake EP/SP, if that's where you're getting your numbers from. If not, present data.
Amiga500 - Wednesday, July 12, 2017 - link
No surprise that the Intel employee is descending to lies and deceit to try and plaster over the chasms! They've also reverted to bribing suppliers to offer Ryzen with only crippled memory speeds too (e.g. pcspecialist.co.uk - try and get a Ryzen system with >2133 MHz memory, yet the SKL-X has up top 3600 MHz memory --- the kicker is - they used to offer Ryzen at up to 3000 MHz memory!). It would seem old habits die hard.Hopefully the readers are wise enough to look at the performance data and make their decisions from that.
If OEMs are willing to bend to Intels dirty dollars, I trust customers will eventually choose to take their business elsewhere. We certainly won't be using pcspecialist again in the near future.
Shankar1962 - Wednesday, July 12, 2017 - link
Look at the picture in this article and see what the big players reported when they upgraded to SkylakeDon't hate a company for the sake of argument. The world we live today from a hardware technology standpoint is because of Intel and respect it
https://www.google.com/amp/s/seekingalpha.com/amp/...
Shankar1962 - Wednesday, July 12, 2017 - link
I agree. Intel has been a data center leader and pioneered for decades now. It has proven track record and overall platform stability consistency and strong portfolio and roadmap. With intel transforming to a data company i see that the best is yet to come as it did smart acquisitions and I believe products with IP from those aquired companies are still nnot fully integrated. Everyone loves an underdog and its clear that everyones excited as someone is getting 5% share and Intel won't be sitting....they did it in the past they will do it again:)0ldman79 - Wednesday, July 12, 2017 - link
I find the power consumption info quite interesting, especially considering the TDP ratings for the processors.The platform makes a difference, though I wonder what the actual difference is. Intel and AMD have been rating their TDP differently for years now.
Atom11 - Wednesday, July 12, 2017 - link
After all these tests we still know nothing about AVX512. According to the specs, the floating point should be about 2x faster on CPU with AVX512 in compare to CPU without AVX512. There should be a clear line between Gcc and Icc. Gcc compiler does not support AVX512 anyway and it otherwise also has a relatively limited vectorization support. Not using Icc means, not using the only compiler which actually supports the Intel hardware features. But it yes, it is a difficult comparison, because you need both Instructions and Software which uses those instructions optimized the best way possible and some users simply don't bother about using optimized software. It would be nice to see comparison between: GCC+ AMD and ICC+Intel. So that only compiler is changed, but also the code is written so that it is possible for it to be efficiently vectorized and threaded. What can I get on Intel, if I use best possible software stack and what can I get on AMD? The current article only answers the question: What can i get on AMD and Intel if I dont bother with software stack and optimization.yuhong - Wednesday, July 12, 2017 - link
Inphi has a press release about shipping 1 million DDR3 LR-DIMM buffers six months before the launch of Haswell-E: https://www.inphi.com/media-center/press-room/pres... I wonder how many they shipped total so far (and also Montage).