Courtesy of Custom PC Review

At Flash Memory Summit, Toshiba was showcasing their latest 15nm 128Gbit MLC NAND wafer that has been developed in partnership with SanDisk. I simply could not resist to calculate the die size as Toshiba/SanDisk has not published it and die size is always the basis of any semiconductor cost analysis. Unfortunately I was too busy running between meetings that I did not take a photo of the wafer, so I am borrowing the picture from Custom PC Review.

Die Size

To estimate the die size, I used the same method as with Samsung's second generation V-NAND. Basically I just calculated the amount of dies in both X and Y axes of the wafer as that gives as an approximation of the die size since we know that the diameter of the wafer is 300mm. 

Bit Density

The 15nm node from Toshiba/SanDisk is extremely competitive. Its bit density is essentially equivalent to Samsung's V-NAND, so it is no wonder that Toshiba and SanDisk are betting heavily on their 15nm node before moving to 3D in early 2016. Compared to other 2D NAND dies, the 15nm node is a clear winner from bit density standpoint as Micron's 16nm MLC does not even come close.

Toshiba's and SanDisk's secret lies in two-sided sense amp and all bit line (ABL) architecture, which reduce the size of the peripheral circuits and sense amplifier, resulting in higher memory array efficiency. Based on my estimation, the array efficiency (i.e. how big portion of the die is dedicated to memory cells) is about 80%, which is typical for a 128Gbit capacity. Higher capacities tend to yield better array efficiency since the peripheral circuitry does not scale as well as the memory cells do, so increasing the die capacity is one of the key solutions in lowering the cost per gigabyte.

Since nobody has yet taken a cross-section of the 15nm die, it is hard to say for sure what Toshiba and SanDisk are doing to shrink the dimensions. There is no mention of high-K dielectrics, so that seems unlikely and if history is any guidance, then Toshiba/SanDisk is simply increasing the aspect ratio by making the floating gate taller to compensate for the smaller feature size and keep the overall floating gate volume similar. That also helps to maintain the gate coupling ratio because the control gate is still wrapped around the floating gate and with a taller floating gate the capacitance between the gates should remain sufficient despite the increasing proximity of the floating gates. 

The production of Toshiba/SanDisk 15nm NAND node is currently ramping up and SSDs based on the new node are expected in Q4'14.

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  • CrazyElf - Friday, August 22, 2014 - link

    Any idea how much the loss in endurance will be compared to 19nm MLC flash? It probably will not affect us in daily use (only for very heavy write loads), but it's an interesting question that is worth looking at. Reply
  • Kristian Vättö - Friday, August 22, 2014 - link

    It should be rated at the same 3,000 P/E cycles -- at least that has been Toshiba's/SanDisk's goal with every die shrink. Reply
  • Infy2 - Friday, August 22, 2014 - link

    I wonder how the durability and cost of manufacture compare to Samsung's new 3D NAND. Reply
  • hojnikb - Friday, August 22, 2014 - link

    Wow, thats significantly better than Microns solution. Hopefully smaller die size will yield in lower street prices for SSDs.

    Are they having any plans to move TLC to 15nm aswell ?
    Reply
  • Kristian Vättö - Friday, August 22, 2014 - link

    15nm TLC production is also ramping up, though it could take a bit longer for it to reach SSD maturity (usually ~2-3 quarters). Reply
  • hojnikb - Friday, August 22, 2014 - link

    Great!

    So i guess its realistical to expect 15nm TLC ssd year or so from now ..
    Reply
  • jjj - Saturday, August 23, 2014 - link

    Interesting that Micron's 128Gb die shrinks only by some 14% from 20nm to 16nm.
    Any clue what size is the second gen 19nm 128Gb die?
    Reply
  • jjj - Saturday, August 23, 2014 - link

    Another observation, the 15nm 128Gb chip is not small enough to fit in a microSD (15x11x1mm with some room for the plastic shell.sp i am assuming very max dies size would be 9x14 so 126mm2) and since the current 128GB is 16 layers plus the controller in a 1mm thick package, it seems unlikely to see bigger microSD from Sandisk ,or anyone else, soon. Reply
  • jjj - Saturday, August 23, 2014 - link

    Unless they use smaller TLC dies and that would be likely Reply
  • hojnikb - Saturday, August 23, 2014 - link

    Or even 4 bits per cell, which was also used by sandisk some time ago. Reply

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