FIRST LOOK: ULi M1697 for Athlon 64/x2
by Wesley Fink on December 13, 2005 12:05 AM EST- Posted in
- CPUs
Overclocking
With an incomplete set of controls for overclocking, it was not possible to test overclocking using our standard OC setups. With production boards due for review very soon, the decision was made to delay OC tests until we reviewed production boards. This will remove the issue of testing with non-standard setups that make comparison of OC performance to previous OC results very difficult.
Memory Stress Testing
Since this is a new chipset, the best setting for tRAS was first determined. With MemTest86, tRAS performance was the same at tRAS settings of 6 to 11, with a bandwidth fall-off at 5 and 12 tRAS settings. This means that any setting from 6 to 11 tRAS will work well with this chipset. We chose to use a tRAS setting of 7 for consistency with other chipsets such as the NVIDIA nForce4 and ATI RD480.
The ULi M1697 Reference easily handles 2-2-2-7-1T timings at stock speed, as do almost any of the current boards for AMD Socket 939 from NVIDIA, SiS, VIA, ATI, and ULi. By default, ULi configured the Command Rate as 1T with a single pair of DIMMs in a dual-channel configuration. Two DIMMs in single channel mode required 2T Command Rate.
Running four double-sided 512MB or 1GB DIMMs is much more demanding than running two DS DIMMs, and ULi behaved as expected. Like every board that we have tested, except the DFI RDX200, we needed to drop the Command Rate to 2T with 4 DS DIMMs. With 4 DIMMs, the M1697 remained stable with the same aggressive 2-2-2-7 timings used for two DS DIMMs.
*7T was determined by MemTest86 benchmarks to deliver the widest bandwidth with the ULi M1697 chipset. While the board would operate at tRAS of 5T or lower, all benchmarks were run at 7T.
With an incomplete set of controls for overclocking, it was not possible to test overclocking using our standard OC setups. With production boards due for review very soon, the decision was made to delay OC tests until we reviewed production boards. This will remove the issue of testing with non-standard setups that make comparison of OC performance to previous OC results very difficult.
Memory Stress Testing
Since this is a new chipset, the best setting for tRAS was first determined. With MemTest86, tRAS performance was the same at tRAS settings of 6 to 11, with a bandwidth fall-off at 5 and 12 tRAS settings. This means that any setting from 6 to 11 tRAS will work well with this chipset. We chose to use a tRAS setting of 7 for consistency with other chipsets such as the NVIDIA nForce4 and ATI RD480.
The ULi M1697 Reference easily handles 2-2-2-7-1T timings at stock speed, as do almost any of the current boards for AMD Socket 939 from NVIDIA, SiS, VIA, ATI, and ULi. By default, ULi configured the Command Rate as 1T with a single pair of DIMMs in a dual-channel configuration. Two DIMMs in single channel mode required 2T Command Rate.
Running four double-sided 512MB or 1GB DIMMs is much more demanding than running two DS DIMMs, and ULi behaved as expected. Like every board that we have tested, except the DFI RDX200, we needed to drop the Command Rate to 2T with 4 DS DIMMs. With 4 DIMMs, the M1697 remained stable with the same aggressive 2-2-2-7 timings used for two DS DIMMs.
| Stable DDR400 Timings - 4 DIMMs (4/4 DIMMs populated) |
|
| Clock Speed: | 200MHz |
| CAS Latency: | 2.0 |
| RAS to CAS Delay: | 2T |
| RAS Precharge: | 7T* |
| Precharge Delay: | 2T |
| Command Rate: | 2T |
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Scarceas - Thursday, December 15, 2005 - link
I presumed that ULI provided Anandtech with the sample to review... if you think about it, there are some wierd angles on that... A big deal like that isn't hammered out in a couple of days. ULI "brass" knew the sale was coming.It's kind of wierd, IMO, to send out stuff for reviews as you're going under.
I suspect that nVidia will sit on any tech they acquire, and not implement it. I was sorely disappointed that they sat on the GigaPixel technology a few years back, and there was of course more from the 3dfx acquisition that they never implemented.
IRQ Conflict - Wednesday, December 14, 2005 - link
Too bad this chipset is doomed before it even gets implemented LOL!http://www.nvidia.com/object/IO_28250.html">LinkPuddleglum - Wednesday, December 14, 2005 - link
https://www.nvidia.com/object/IO_28250.html">https://www.nvidia.com/object/IO_28250.htmlTorched - Wednesday, December 14, 2005 - link
Bad link on above post. You can read about Nvidia buying out ULi http://www.theinquirer.net/?article=28333">hereIRQ Conflict - Wednesday, December 14, 2005 - link
wierd, it was working yesterday? Oh well nVidia's following M$'s lead again. I can still smell the embers of the 3dfx acquasition.Peter - Tuesday, December 13, 2005 - link
And yet again, we're seeing Anandtech experts (?) evaluate the RAM controller properties of an AMD64 chipset.Hello?
The RAM controller is in the CPU, folks. Time to acknowledge that and skip that step in a chipset review.
Puddleglum - Wednesday, December 14, 2005 - link
Peter, this is what you were referencing:I don't see the words "controller" or "chipset" in there, and yet you say that the article evaluates the RAM controller properties of the chipsets. What he said about the lack of memory voltage adjustments was not referencing the chipset, but the method that Anandtech uses to overclock their boards.How did you come to think that the article mentioned the RAM controller?
Peter - Thursday, December 15, 2005 - link
I'm referring to the following statements on page 4:>Memory Stress Testing: Since this is a new chipset, the best setting for tRAS was first determined.
>This means that any setting from 6 to 11 tRAS will work well with this chipset.
>*7T was determined by MemTest86 benchmarks to deliver the widest bandwidth with the ULi M1697 chipset.
For anyone who's looked at the block diagram on page 2, it should be bleeding obvious that the RAM isn't the chipset's business at all.
Cygni - Tuesday, December 13, 2005 - link
Uhhhhh... havent used many A64 boards lately? ;) The ability to run low latency timings is very highly regulated by the board and chipset. You cant just drop any stick of ram in any board and get identical timings.The memory controller may be on the chip itself, but this doesnt eliminate the board and chipset from the equation whatsoever.
Peter - Wednesday, December 14, 2005 - link
AMD64 architecture totally eliminates the chipset from anything that is even remotely to do with the RAM bus. That's the point, and you're not getting it either.