The Silvermont Module and Caches

Like AMD’s Bobcat and Jaguar designs, Silvermont is modular. The default Silvermont building block is a two-core/two-thread design. Each core is equally capable and there’s no shared execution hardware. Silvermont supports up to 8-core configurations by placing multiple modules in an SoC.

 

Each module features a shared 1MB L2 cache, a 2x increase over the core:cache ratio of existing Atom based processors. Despite the larger L2, access latency is reduced by 2 clocks. The default module size gives you clear indication as to where Intel saw Silvermont being most useful. At the time of its inception, I doubt Intel anticipated such a quick shift to quad-core smartphones otherwise it might’ve considered a larger default module size.

L1 cache sizes/latencies haven’t changed. Each Silvermont core features a 32KB L1 data cache and 24KB L1 instruction cache.

Silvermont Supports Independent Core Frequencies: Vindication for Qualcomm?

In all Intel Core based microprocessors, all cores are tied to the same frequency - those that aren’t in use are simply shut off (power gated) to save power. Qualcomm’s multi-core architecture has always supported independent frequency planes for all CPUs in the SoC, something that Intel has always insisted was a bad idea. In a strange turn of events, Intel joins Qualcomm in offering the ability to run each core in a Silvermont module at its own independent frequency. You could have one Silvermont core running at 2.4GHz and another one running at 1.2GHz. Unlike Qualcomm’s implementation, Silvermont’s independent frequency planes are optional. In a split frequency case, the shared L2 cache always runs at the higher of the two frequencies. Intel believes the flexibility might be useful in some low cost Silvermont implementations where the OS actively uses core pinning to keep threads parked on specific cores. I doubt we’ll see this on most tablet or smartphone implementations of the design.

From FSB to IDI

Atom and all of its derivatives have a nasty secret: they never really got any latency benefits from integrating a memory controller on die. The first implementation of Atom was a 3-chip solution, with the memory controller contained within the North Bridge. The CPU talked to the North Bridge via a low power Front Side Bus implementation. This setup should sound familiar to anyone who remembers Intel architectures from the late 90s up to the mid 2000s. In pursuit of integration, Intel eventually brought the memory controller and graphics onto a single die. Historically, bringing the memory controller onto the same die as the CPU came with a nice reduction in access latency - unfortunately Atom never enjoyed this. The reasoning? Atom never ditched the FSB interface.

Even though Atom integrated a memory controller, the design logically looked like it did before. Integration only saved Intel space and power, it never granted it any performance. I suspect Intel did this to keep costs down. I noticed the problem years ago but completely forgot about it since it’s been so long. Thankfully, with Silvermont the FSB interface is completely gone.

Silvermont instead integrates the same in-die interconnect (IDI) that is used in the big Core based processors. Intel’s IDI is a lightweight point to point interface that’s far lower overhead than the old FSB architecture. The move to IDI and the changes to the system fabric are enough to improve single threaded performance by low double digits. The gains are even bigger in heavily threaded scenarios.

Another benefit of moving away from a very old FSB to IDI is increased flexibility in how Silvermont can clock up/down. Previously there were fixed FSB:CPU ratios that had to be maintained at all times, which meant the FSB had to be lowered significantly when the CPU was running at very low frequencies. In Silvermont, the IDI and CPU frequencies are largely decoupled - enabling good bandwidth out of the cores even at low frequency levels.

The System Agent

Silvermont gains an updated system agent (read: North Bridge) that’s much better at allowing access to main memory. In all previous generation Atom architectures, virtually all memory accesses had to happen in-order (Clover Trail had some minor OoO improvements here). Silvermont’s system agent now allows reordering of memory requests coming in from all consumers/producers (e.g. CPU cores, GPU, etc...) to optimize for performance and quality of service (e.g. ensuring graphics demands on memory can regularly pre-empt CPU requests when necessary).

ISA, IPC & Frequency SoCs and Graphics, Penryn-Class Performance
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  • Kevin G - Monday, May 6, 2013 - link

    Actually I've gotten the impression from Anandtech that Intel has been so tardy on providing chips for the mobile market that they may have lost the fight before even showing up. Intel may have good designs and the best foundries but that doesn't matter if ARM competitors arrive first with 'good enough' designs to gobble up all the market share. There is a likely a bit of frustration here constantly hearing about good tech that never reaches its potential.

    There was the recent line in the news article here about Intel's CEO choice about how Intel is foundry that makes x86 processors. That choice was likely selected due to Intel's future of becoming an open foundry to 3rd party designs. Intel has done this to a limited degree already. They recently signed a deal with Microsemi to manufacture FPGA's on Intel's 22 nm process. Presumably future Microsemi ARM based SoC + FGPA chips will also be manufactured by Intel as well.
  • Kidster3001 - Tuesday, May 7, 2013 - link

    Intel has publicly stated that it's foundry business will never make products for a competitor. That means no ARM SoC's in Intel fabs.
  • Kevin G - Tuesday, May 7, 2013 - link

    Intel isn't active in the FPGA area, well there than manufacturing them for a handful of 3rd parties. The inclusion of an ARM core inside a SOC + FGPA design wouldn't be seen as a direct competitor. Indirectly it definitely would be a competitor but then again just the FPGA alone would be an indirect competitor.
  • name99 - Monday, May 6, 2013 - link

    Actually the REAL history is
    - Intel article appears. All the ARM fans whine about how unfair and awful it is, and how it refers to a chip that will only be released in six months.
    - ARM article appears. All the Intel fans whine about how unfair and awful it is, and how it refers to a chip that will only be released in six months.
    - Apple (CPU) article appears. Non-Apple ARM and Intel fans both whine about how unfair it is (because of tight OS integration or something, and Apple is closed so it doesn't count).

    Repeat every six months...
  • Bob Todd - Tuesday, May 7, 2013 - link

    Winner winner chicken dinner. I love how butt hurt people get about any article comparing CPU or GPU performance of two or more competitors (speculatively or not). I have devices with Krait, Swift, Tegra 3, Bobcat, Llano, Ivy Bridge, etc. They all made sense at the time for one reason or another or I wouldn't have them. I'm excited about Slivermont, just like I'm excited about Jaguar, and whatever Apple/Samsung/Qualcom/Nvidia cook up next on the ARM side. It's an awesome time to be into mobile gadgets. Now I'll sit back and laugh at the e-peen waiving misguided fanboyism...
  • axien86 - Monday, May 6, 2013 - link


    Acer is shipping new V5 ultraportables based on AMD's Jaguar high performance per watt technology in 30 days. AMD is 10 to 20 times smaller than Intel, but with design wins from Sony, Microsoft and now many other OEMs, they are delivering real performance for real value.

    By contrast Intel really has nothing to show, but endless public relations to compensate for a history of company that has been upstaged by smaller companies like AMD in forging real innovations in computing.
  • A5 - Monday, May 6, 2013 - link

    If by "high performance per watt" you mean "less performance in a higher TDP" than sure. Intel trounces AMD in notebooks for a reason.

    As for the Sony/MS stuff, I doubt Intel even bid for those contracts.
  • kyuu - Monday, May 6, 2013 - link

    I hope you're kidding. Bobcat-based designs have been superior to Atom for forever, and if you take graphics performance into account, then Atom has been nothing short of laughable. I wouldn't be surprised if Silvermont beats Jaguar in CPU performance, but it'll be a small delta, and Jaguar is coming out a full half-year ahead of Silvermont.

    It's also nice that Intel might get GPU performance around the level of the iPad 4's SoC by the end of the year, but I believe AMD's mobile graphics already handily surpass that and the ARM world will have moved on to solutions that handily surpass that by then as well. So, yet again, Intel will be well behind the GPU curve. It won't be laughably bad anymore, though, at least.

    And I really love that last line. "Intel didn't get some design wins? Well, psh, they totally didn't even want those anyway."
  • kyuu - Monday, May 6, 2013 - link

    Oh, and also not sure why you brought notebooks up when we're talking about architectures for very low-power devices like tablets, netbooks, and maybe some ultrathins. No one would claim that Trinity/Richland is at the same level of CPU performance as Ivy Bridge/Haswell. Personally, though, I'd still prefer an AMD solution for a notebook for the superior graphics, lower price, and more-than-adequate CPU performance.
  • xTRICKYxx - Tuesday, May 7, 2013 - link

    This is where I want AMD to come into play. Their low power CPU's are so much better than Atom ever was, and always had superior graphics.

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