Availability and Controller support

Just to make this clear, TLC isn't anything new. For example Hynix had a 32Gb 48nm TLC die in 2008. This is because TLC was originally used for devices like USB flash drives, where its poor endurance would be negligible. Most SSD OEMs have been toying with TLC SSDs for at least a year now but we haven't seen any commercial products. OCZ had originally planned to introduce its first TLC based SSD in the Q1 2012, however TLC pricing simply hasn't made sense yet. Unless OCZ can leverage a significant cost savings over 2-bit-per-cell MLC, the added headaches of bringing a lower performing TLC part to market don't make sense.

However there's still significant motivation to migrate towards TLC NAND. Further bringing down costs, particularly for consumer SSDs aimed at light, particularly read heavy workloads makes a lot of sense. Increasing pressure from Intel to deliver cheaper SSD enabled Ultrabooks, and Apple's desire to move all mainstream Macs to solid state storage are two major motivations. MLC NAND pricing will eventually get low enough to meet these (and more) needs, but TLC definitely accelerates the process.

TLC does require controller and firmware support. In the client SSD space only OCZ has been aggressive with announcing that its Indilinx Everest controller supports 3-bit-per-cell NAND. 

Adding controller support for an extra bit per cell is more than just updating the datasheet and claiming it works. The ECC engine needs to be updated as the controller will face more frequent and more severe errors with TLC NAND (and its associated lower endurance rating).

Maintaining low write amplification is even more important with TLC NAND. With significantly fewer available program/erase cycles, burning through them due to high write amplification isn't acceptible. While NAND endurance isn't really an issue for most client MLC drives, it may be an issue for TLC based drives. 

Weaknesses of TLC: One Step Worse than MLC Final Thoughts
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  • aguilpa1 - Thursday, February 23, 2012 - link

    I feel all warm and technical inside. Reply
  • Taft12 - Thursday, February 23, 2012 - link

    "However, there have been quite a few widespread firmware issues, such as SF-2281 BSOD and Intel 320 Series 8MB bugs"

    No list of SSD firmware cockups is complete without mentioning the Kingston V200 abysmal write performance:

    http://forum.notebookreview.com/solid-state-drives...

    The fact that they're handing out V+ left and right to those requesting RMAs suggests to me the problem will never get fixed.
    Reply
  • dorion - Thursday, February 23, 2012 - link

    I'm having trouble understanding why the density gain from TLC is only linear and not quadratic. It seems like the web is crawling with a bunch of articles today saying the SLC -> MLC -> TLC density gain is 16 -> 32 -> 48. It should be 16 -> 32 -> 64. Am I right? Or is there something I'm not getting? Is it part of the ECC like Gray code? Reply
  • Death666Angel - Thursday, February 23, 2012 - link

    Huh?
    SLC = 1 Cell, 1 bit
    MLC = 1 Cell, 2 bits
    TLC = 1 Cell, 3 bits
    You seem to think that TLC is 1 Cell, 4 bits, which it is not. Not sure why you would think that, though.
    Reply
  • JarredWalton - Thursday, February 23, 2012 - link

    It's simple multiples, not powers. SLC stores one bit per cell, MLC is two, and TLC is three. MLC is thus twice the capacity of SLC, but TLC is only three times the capacity, not four. The power of two increase comes in the number of states to check: SLC checks two (0/1), MLC checks four (00,01,10,11), and TLC checks eight (000, 0001..., 110, 111). If someone were to try and do QLC they would need to check sixteen states, endurance would really plummet, and performance would be worse as well. Reply
  • dorion - Thursday, February 23, 2012 - link

    I cant believe I overlooked the difference between bits you can store and how high you can count with a certain number of bits. Reply
  • ionis - Friday, February 24, 2012 - link

    That only proves it should go 16->32->64.

    1 bit - 2 states - 16 Gb
    2 bits - 4 states (double the previous) - 32Gb
    3 bits - 8 states (double the the previous) - should be 64Gb not 48Gb. I'm still confused how the author got 48Gb.
    Reply
  • JMC2000 - Friday, February 24, 2012 - link

    The number of bits per cell is not equal to the number of voltage states. I'm not very knowledgeable in how NAND is produced, but I think the increase in voltage states by x2 per bit may have to do with the need for differentiation to write/erase each bit. Reply
  • ionis - Friday, February 24, 2012 - link

    The article explicitly states that the number of bits per cell is equal to the number of voltage states. Reply
  • JMC2000 - Friday, February 24, 2012 - link

    Do you mean this paragraph?

    "Rather than shrinking the die to improve density/capacity, TLC (like MLC) increases the number of bits per cell. In our SSD Anthology article, Anand described how SLC and MLC flash work, and TLC works the same way but takes things a step further. Normally, you apply a voltage to a cell and keep increasing it until you reach a point where the result is far enough from the "off" state that you now consider the cell as being "on". This is how SLC works, storing one bit per cell. For MLC, you store two bits per cell, which means instead of two voltage states (0 and 1) you have four states (00, 01, 10, 11). TLC takes that a step further and stores three bits per cell, or eight voltage states (000, 001, 010, 011, 100, 101, 110, and 111). We will take a deeper look into voltage states and how they work in the next page."

    Or this one?

    "SLC only has two program states, "0" and "1". Hence either a high or low voltage is required. When the amount of bits goes up, you need more voltage stages. With MLC, there are four states, and eight states with TLC. The problem is that the silicon oxide layer is only about 10nm thick and it's not immortal; it wears out every time it's used in the tunneling process. When the silicon oxide layer wears out, the atomic bonds break and during the tunneling process, some electrons may get trapped inside the silicon oxide. This builds up negative charge in the silicon oxide, which negates some of the the control gate voltage."

    Nowhere in the article does it state that the number of bits per transistor is equal to the number of voltage states.
    Reply

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