With the week almost over, what has been undoubtedly the most exciting conference in the past several months has come to a close. Thanks to Intel and also AMD, this week has been extremely interesting and is a great introduction to the products that will be coming out later this year and into 2003. This will be one of our two final pieces on the conference after which things will return to normal as I begin the benchmark frenzy on some of the hardware and technologies discussed over the past few days.

AMD and Intel talk CPUs

We learned a bit more about the future of both AMD's and Intel's CPUs from talking to representatives from both companies as well as piecing together a bit of information on our own.

First let's start with AMD; remember Barton, the 0.13-micron Silicon on Insulator part? The purpose for that chip was to enable the 0.13-micron SOI technology and with ClawHammer moving along as planned, AMD is reevaluating its need in the market. As we've speculated for quite a while, it doesn't seem as if there will be any major architectural improvements with the 0.13-micron Thoroughbred core although AMD has told us that they aren't opposed to evaluating any changes that could be made. The only one we can think of is adding additional cache to the die but considering that AMD's performance is already very strong and that they are still manufacturing on 8" wafers, keeping their die as small as possible is probably in their best interests. As far as Hammer naming goes we have no reason to believe that the desktop version won't be branded as some sort of Athlon although the enterprise level solutions may get a new brand.

On the Intel side of things we completely forgot to mention one very important characteristic of Prescott yesterday. If you'll remember back to our BBUL technology article we gave a little preview of the FSB frequencies of future Intel processors - with Prescott coming in with an 800MHz FSB (presumably 200MHz quad-pumped). As far as other enhancements go, the move to a 0.09-micron manufacturing process will reduce the current Northwood die size by about half leaving quite a bit of room for additional architectural enhancements. Some theories we had included offering more cache (768KB or 1MB?) and maybe even moving to 32-bit ALUs instead of the current 16-bit units. The latter would make sense since Intel has been demonstrating high-speed 32-bit ALUs for quite a while now.

If both of these hold true, it means that the only CPUs that will be released over the next few months will be simply speed bumps until the Hammer is officially released.


The world's first display of the upcoming Banias chipset (Odem) running with a Northwood

During Anand Chandrasekher's keynote, he demonstrated the world's first Banias platform - the chipset is codenamed Odem. As you'll remember from previous IDF conferences, Banias is Intel's first CPU that has been designed from the ground up to be a mobile CPU. Designed by Intel's team in Israel, Banias is supposed to truly bring high performance and mobility together in a CPU aimed at making the perfect notebook. Banias will be a departure from anything we've ever seen from Intel in the past and will have quite a bit to do with wireless technology but we'll leave it at that until closer to Banias' 2003 release.

Forget Serial ATA, it's time for Serial ATA II

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