The Intel Developer Forum entered day 2 today, bringing with it a bit more info regarding Intel's vision of the future. The day began with the usual keynote, where Ron Smith, vice president and general manager of wireless communications and computing group at Intel was able to demonstrate Intel's new XScale microarchitecture
Targeted at hand held devices and smart appliance, the XScale microarchitecture is based on Intel's current StrongARM technology that is widely incorporated in products today, such as the empeg as well as the Compaq iPaq. XScale microarchitecture promises to bring a whole new world to these devices, as the beta silicon demonstrated was able to show not only extreme speed but also very low power consumption.
Perhaps the most interesting part of the keynote was when Smith was actually able to show of the new product. Running Drystone 2.1 benchmark, the small development platform featuring the beta XScale core technology was first displayed running at 600 MHz and consuming .5 watts of power. Next Smith showed the dynamic frequency and voltage capabilities of the XScale processor core, dynamically pushing the chip up to 800 MHz with less than 1 watt of power. The chip was now running at over 1000 mips (million instructions per second), surpassing the watt per mips ratio seen an any prior product. Next was to push the XScale core up even more, reaching 1 GHz with 1.75 watts of power consumption and 1270 mips, a figure that seemed quite impressive to us, considering that the chip is targeted at low power, high performance hand held systems. The possibilities that come with having such a high performance, low cost, low power chip seem endless, with the prospect of running MPEG2 quality video on a hand held not too far away. Intel stated that the XScale core used "super pipeline technology," that allowed for the reaching of high clock speeds. This could be in reference to increasing the length of the pipeline and lowering the effective number of instructions per clock in order to reach a higher operating frequency. This would be much like what Intel is calling their "Hyper Pipelined Technology" which is used to help increase the operating frequency of the upcoming Pentium 4 processor.
Next was a demonstration of not how fast the XScale can go, but rather how slow. By taking into account the fact that power is equal to capacitance times frequency times the square of the voltage, XScale's dynamic voltage and frequency adjustments have the possibility to produce a very low power consuming chip. The beta XScale core demonstrated, based on a .18 micron architecture, was able to run at a mere .055 watts at a speed of 50 MHz. Still able to process 250 mips, the XScale chip at this speed is able to be run off a single AA battery. Although the 250 mips number coming from the 50 MHz XScale core may not seem very fast in comparison to the 1270 mips of the 1 GHz XScale chip, when it is compared it to the .25 mips of the IBM PC/XT or the 100 mips speed of the early Pentium chips, the 250 mips is quite impressive, especially when one considers the low power consumption of the chip at this speed.
It was a bit odd to contrast the presentation of Intel's mobile section from Albert Yu yesterday with the XScale technology demonstration of today. If you recall from our IDF Fall 2000 Day 1 report, yesterday Yu stressed that the power consumption of the CPU in notebooks is not of concern, as the CPU only takes up a small amount of power when compared to other parts of the system (more on this later). Today the scene was a bit different, with Smith stressing the very low power consumption of the XScale microarchitecture as a result of its dynamic voltage management. Sure, the XScale technology is NOT target for notebook solutions by any means, but with the line between notebooks and hand helds becoming less and less defined it only seems logical that the issues with the two systems must be related.