Toshiba's 2nd gen HD-DVD Player

An unexpected gem on stage with Otellini at today's keynote was an early version of Toshiba's 2nd generation HD-DVD player. We're expecting significant improvements to start up time with Toshiba's 2nd gen player, and Otellini confirmed that the player would be available with a sub-$500 price tag.


The 2nd generation Toshiba HD-DVD set top player is barely visible in the lower left of the picture

The 2nd generation player does still use Intel silicon and given the reduction in vertical height of the device, we're assuming that Toshiba is now using a Core based processor rather than the NetBurst based Pentium 4 in the first generation player.

The Only Worthwhile Viiv Related Feature

Intel devoted a small portion of the morning's keynotes to an update on Viiv, which honestly wasn't much at all. Viiv's reception has not been anywhere nearly as strong as Centrino, and we don't expect it to get any better until Intel can deliver something that is substantially more than what you can already do with a good MCE PC. Right now Viiv is more marketing and fluff than features and technology, and as such it's not something that's particularly interesting to us. There was however one interesting demo of a feature that is supported by Viiv systems from ClickStar:

ClickStar has committed to delivering, within two weeks of the film's theatrical release, an online downloadable copy of the movie 10 Items or Less. As we inch towards a broadband delivery model for movies, simultaneous or near simultaneous online and theatrical releases of movies will become reality. We're still a bit away from that reality, but the ClickStar solution is at least a step in the right direction.

Intel's Answer to Cell: The Teraflop Chip UMPC Update
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  • GNStudios - Wednesday, September 27, 2006 - link

    Is Quad-core going to much faster than dual-core, like when core 2 duo came?

    Reply is appriciated. :-)
  • Niv KA - Wednesday, September 27, 2006 - link

    I have reasons to belive that whatever will come after Gesher will be very different from what we have today. Gesher is translated to brigde in Hebrew. Therefore I have reason to belive that what ever Gesher will be, it will be a transition to a new technology.

    I know I repeated myself a few times.

    -- Niv K Aharonovich
  • sprockkets - Wednesday, September 27, 2006 - link

    It used a Netburst and most likely a prescott core processor to operate WTF?

  • GhandiInstinct - Wednesday, September 27, 2006 - link

    The day, in a press conference, the day in which multi-code is mastered in software, that we see in a video game demo, a full fledged Torando tearing down a metropolis.
  • yacoub - Tuesday, September 26, 2006 - link

    Good coverage so far: Lots of pics, informative text between them, and lots of new tech incoming from Intel! woot
  • porkster - Tuesday, September 26, 2006 - link

    Any news on Santa Rosa chipsets? I couldn't see them in the road map.
  • porkster - Tuesday, September 26, 2006 - link

    Intel and Microsoft have no idea when it comes to what people will buy and can afford.

    Ye, like in the picture we are all going to buy 3 and 4 of these flop devices for our cars. Without these devices being under $200, no one will take then serious.

    It seems like anytime someone bring up a portable, they have to use an expensive cpu in it. I can't see why you can't jsut echo a wifi'ed screen from another computer at home or in the car. A device the is a terminal, not a separate computer.
  • mino - Tuesday, September 26, 2006 - link

    "Years ago Micron talked about equipping a chipset with an on-die L3 cache to help improve performance, and it's looking like Intel will be doing just that"

    IBM has it since 2002 ... ;)

    BTW it was the main reason IMB did not jump on Opteron so eagerly. They have a chipset hugely hugely superior to Itel's Truland since 2003. Game over period.

    That snoop cache is the thing which brought SC Nocona Xeons on par with SC Opterons in 4P-8P scenarios!!!

    First Intel DC Smithfield _IS_ single-die, it is just glued together but single-die. The reason being MCM puts huge strain on FSB so they put an arbitter on a glued chip, to help achieve even mediocre 800FSB on their chipsets of the time.
  • mino - Tuesday, September 26, 2006 - link

    "Years ago Micron talked about equipping a chipset with an on-die L3 cache to help improve performance, and it's looking like Intel will be doing just that"

    IBM has it since 2002 ... ;)

    BTW it was the main reason IMB did not jump on Opteron so eagerly. They have a chipset hugely hugely superior to Itel's Truland since 2003. Game over period.

    That snoop cache is the thing which brought SC Nocona Xeons on par with SC Opterons in 4P-8P scenarios!!!

    BTW First Intel DC Smithfield _IS_ single-die, it is just glued together but single-die. The reason being MCM puts huge strain on FSB so they put an arbitter on a glued chip, to help achieve even mediocre 800FSB on their chipsets of the time.
  • mino - Tuesday, September 26, 2006 - link

    screwed title, if posiible please delete/vote out. Thanks.

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