A quick news piece on information coming out of Intel’s annual Investor Day in California. As confirmed to Ashraf Eassa by Intel at the event, Intel’s 8th Generation Core microarchitecture will remain on the 14nm node. This is an interesting development with the recent launch of Intel’s 7th Generation Core products being touted as the ‘optimization’ behind the new ‘Process-Architecture-Optimization’ three-stage cadence that had replaced the old ‘tick-tock’ cadence. With Intel stringing out 14nm (or at least, an improved variant of 14nm as we’ve seen on 7th Gen) for another generation, it makes us wonder where exactly Intel can promise future performance or efficiency gains on the design unless they start implementing microarchitecture changes.

Despite this, if you were to believe supposed ‘leaked’ roadmaps (which we haven’t confirmed from a second source as of yet), the 8th Generation product ‘Cannon Lake’ is more geared towards the Y and U part of Intel’s roadmap. This would ring true with a mobile first strategy that Intel has mirrored with recent generations such that the smaller, low power chips are off the production line for a new product first, however we'd also expect 10nm to also be in the smaller chips first too (as demonstrated at CES). Where Cannon Lake will end up in the desktop or enterprise segment however remains to be seen. To put something a bit more solid into this, Ashraf also mentioned words from Dr. Venkata ‘Murthy’ Renduchintala, VP and GM of Client and IoT:

‘Murthy referred to it at the event, process tech use will be ‘fluid’ based on segment’.

If one read too much into this, we may start seeing a blend of process nodes for different segments at the same time for different areas of the market. We already do have that to some extent with the mainstream CPUs and the HEDT/Xeon families, but this phrasing seems that we might get another split between consumer products or consumer and enterprise. We may get to a point where Intel's 'Gen' naming scheme for its CPUs covers two or more process node variants.

Speaking of the Enterprise segment, another bit of information has also surfaced, coming from a slide during a talk by Diane Bryant (EVP/GM of Data Center) and posted online by Ashraf. The slide contains the words ‘Data center first for next process node’

We can either talk about process node in terms of the ‘number’, either 14nm/10nm/7nm, or by variants within that process (high power, high efficiency). One might suspect that this means Intel is moving hard and fast with 10nm for Xeons and big computing projects, despite showing off 10nm silicon at CES earlier this year. That being said, it’s important to remember that the data center market is large, and includes high-density systems with many cores, such as Atom cores, and Intel did recently open up its 10nm foundry business to ARM Artisan IP projects. So while the slide does say ‘Data center first’, it might be referring to DC projects based on ARM IP in that segment rather than big 4-24+ core Xeons. At this stage of the game it is hard to tell.

On top of all this, Intel still has extreme confidence in its foundry business. An image posted by Dick James of Siliconics from the livestream shows Intel expects to have a three-year process node advantage when its competitors (Samsung, TSMC) start launching 10nm:

I’ve been brief with this news for a reason - at this point there are a lot of balls in the air with many different ways to take this information, and the Investor Day is winding down on talks and finishing with smaller 1-on-1 meetings. We may get further clarification on this news as the day goes on.

Update 1: On speaking with Diane Bryant, the 'data center gets new nodes first' is going to be achieved by using multiple small dies on a single package. But rather than use a multi-chip package as in previous multi-core products, Intel will be using EMIB as demonstrated at ISSCC: an MCP/2.5D interposer-like design with an Embedded Multi-Die Interconnect Bridge (EMIB).


An Intel Slide from ISSCC, via PC Watch

Initially EMIB was thought of as a technology relating to Intel's acquisition of Altera and potential future embedded FPGA designs, and given the slide above and comments made at the Investor Day, it seems there are other plans for this technology too. The benefit of using multiple smaller dies over a large monolithic 600mm2 die is typically related to cost and yield, however the EMIB technology also has to be up to par and there may be a latency or compatibility trade-off.

Source: Intel, @TMFChipFool

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  • Yojimbo - Thursday, February 09, 2017 - link

    "Data centers first to new nodes".

    Does this mean Intel is going to accept lower margins on its data center hardware in order to chase the growth that exists in that segment and to try to stem off competition?
    Reply
  • witeken - Friday, February 10, 2017 - link

    You are correct, D. Bryant has said they expect operating margin the shrink from in the high-40 % to low-40%. The EMIB technology to slip the die in chiplets is a really, really big deal to achieve this data center first strategy, which in itself is already a monumental and underrated change of business. Compare this to TSMC and Samsung, who go mobile first. Intel is now doing opposite. Reply
  • Gondalf - Friday, February 10, 2017 - link

    You are wrong. Intel will go mobile (CORE M and 15W line) and datacenter first with 10nm. LIke have done on 14nm. Nothing is changed. This time Intel refuse to delay datacenter SKUs and adopt the multidie approach to stay ahead the competition in spite the impossibility to manufacture large die SKUs at the beginning of the new node ramp. EMIB was patented for this in 2014.
    I don't see any monumental change of business, so sorry
    Reply
  • witeken - Friday, February 10, 2017 - link

    Diane Bryant has said that this change will start with 10nm++, and then 7nm as the first full node. This is, she said, because it takes many years to build these products, so the development for the first 10nm products are already well under way. Reply
  • Yojimbo - Friday, February 10, 2017 - link

    Intel didn't go data center first with 14nm. 14nm Xeon E5s didn't come out until the beginning of 2016 whereas 14nm was used on other products (lower power, mobility parts) as early as late 2014. Mobile Core i processors used it in early 2015 and desktop Core i processors used it in the middle of 2015. Reply
  • Alexvrb - Saturday, February 11, 2017 - link

    This is true but witeken is saying that they're doing the opposite of mobile-first competition. Intel is definitely shifting priorities, but they are still going to put a lot of effort towards mobile. So if mobile is their number two priority, I'd hardly say that's the "opposite" of Sammy et al.

    Either way every time I see one of those Intel cloud/server commercials I can't help but think Naples must concern them a little.
    Reply
  • nils_ - Wednesday, February 15, 2017 - link

    Don't forget about Broadwell-DE in mid-late 2015, which pretty much killed most ARM offerings in the crib. Reply
  • name99 - Friday, February 10, 2017 - link

    To me this looks like a desperate action, not a careful plan. It suggests that they expect 10nm yields to be so bad for a while that they simply will not be able to ship mobile volumes, even if they repeat the pathetic multi-quarter extended rollout of Broadwell, one SKU at a time.

    Even assuming EMIB works wonderfully and delivers something like what it claims, client delivers twice the revenue of data center, and there's much more value to a better performing chip (faster single-threaded, and lower power) in mobile than in data center (ie more people will pay more for it).

    They're going data center first because they HAVE TO, not because they want to.
    Reply
  • iwod - Friday, February 10, 2017 - link

    This implies either IBM Power 8 is really going to be a threat or AMD Zen is finally catching up. Reply
  • Nagorak - Sunday, February 12, 2017 - link

    Or both. Intel's performance lead suddenly looks to be in serious danger. Reply

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