AnandTech: Fall IDF 2006 - Day 1: 45/65nm, UMPC Update and Quad-Core

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Fall IDF 2006 - Day 1: 45/65nm, UMPC Update and Quad-Core

Date: September 26th, 2006
Topic: CPU & Chipset
Manufacturer: Intel
Author: Anand Shimpi & Larry Barber

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Intel's Paul Otellini kicked off this year's Fall IDF with the first keynote of the show and as always, we've got coverage of the event:

Yes, that's a Mac on stage at an IDF keynote

Paul's keynote marked the first time an Apple representative was on stage at an Intel IDF keynote as Apple's Phil Schiller tooted Apple's horn for completing the Intel processor transition:

There were no new Apple announcements and the portion of the keynote that covered Apple was relatively useless, but it was an interesting moment to note just for its historical significance as the first real Apple presence at an IDF keynote.

Halfway to 65nm

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12 Comments - Last by GNStudios, 1231 days ago

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At this rate the machines will rise sooner than we thought by PeteRoy, 1232 days ago

Good to hear that there's still more to come.

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by gersson, 1232 days ago

I would also like to make a generic statement

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"Years ago Micron talked about equipping a chipset with an on-die L3 cache to he by mino, 1232 days ago

"Years ago Micron talked about equipping a chipset with an on-die L3 cache to help improve performance, and it's looking like Intel will be doing just that"

IBM has it since 2002 ... ;)

BTW it was the main reason IMB did not jump on Opteron so eagerly. They have a chipset hugely hugely superior to Itel's Truland since 2003. Game over period.

That snoop cache is the thing which brought SC Nocona Xeons on par with SC Opterons in 4P-8P scenarios!!!

BTW First Intel DC Smithfield _IS_ single-die, it is just glued together but single-die. The reason being MCM puts huge strain on FSB so they put an arbitter on a glued chip, to help achieve even mediocre 800FSB on their chipsets of the time.

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:oops: by mino, 1232 days ago

screwed title, if posiible please delete/vote out. Thanks.

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First INTC DC, 4P/8P stuff mistakes by mino, 1232 days ago

"Years ago Micron talked about equipping a chipset with an on-die L3 cache to help improve performance, and it's looking like Intel will be doing just that"

IBM has it since 2002 ... ;)

BTW it was the main reason IMB did not jump on Opteron so eagerly. They have a chipset hugely hugely superior to Itel's Truland since 2003. Game over period.

That snoop cache is the thing which brought SC Nocona Xeons on par with SC Opterons in 4P-8P scenarios!!!

First Intel DC Smithfield _IS_ single-die, it is just glued together but single-die. The reason being MCM puts huge strain on FSB so they put an arbitter on a glued chip, to help achieve even mediocre 800FSB on their chipsets of the time.

Reply

No Idea. UMPC's by porkster, 1232 days ago

Intel and Microsoft have no idea when it comes to what people will buy and can afford.

Ye, like in the picture we are all going to buy 3 and 4 of these flop devices for our cars. Without these devices being under $200, no one will take then serious.

It seems like anytime someone bring up a portable, they have to use an expensive cpu in it. I can't see why you can't jsut echo a wifi'ed screen from another computer at home or in the car. A device the is a terminal, not a separate computer.

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Any News on Santa Rosa Chipsets? by porkster, 1232 days ago

Any news on Santa Rosa chipsets? I couldn't see them in the road map.

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sweet. by yacoub, 1231 days ago

Good coverage so far: Lots of pics, informative text between them, and lots of new tech incoming from Intel! woot

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I CANNOT WAIT! by GhandiInstinct, 1231 days ago

The day, in a press conference, the day in which multi-code is mastered in software, that we see in a video game demo, a full fledged Torando tearing down a metropolis.

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HD DVD by sprockkets, 1231 days ago

It used a Netburst and most likely a prescott core processor to operate WTF?

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