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The little cores in this scenario are virtually sitting idle as for most of the time we don't have much activity placed on them. 

The big core activity in this scenario is interesting: While we see all 4 CPUs having activity placed on them, the threads never manage to exceed ~30-35% load capacity. This is also quite the extreme scenario in terms of the power state distribution: It seems the load on the cores is so fine-grained that the CPU Idle system greatly prefers to choose clock-gating state instead of the power-collapse state. The CPU frequency points out that we're also dealing with some very burst loads as we see the cluster clock up to 1.7GHz. 

Again, in terms of actual total run-queue depth this task could have easily been done by a 2-core SoC such as Apple's A6/7/8 without losing on performance. What one has to consider though is that the per-CPU load on such a SoC would be much higher, requiring higher single-CPU performance or frequency. Because the app actually manages to spread out the load equally over 4 CPUs, it should actually be able to take advantage of pararellism for the sake of power efficiency instead of performance.

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  • modulusshift - Tuesday, September 1, 2015 - link

    Heck yes. And of course I'm interested if anything like this is even remotely possible for Apple hardware, though likely it would require jailbreaks, at least.
  • Andrei Frumusanu - Tuesday, September 1, 2015 - link

    Unfortunately basically none of the metrics measured here would be possible to extract from an iOS device.
  • TylerGrunter - Tuesday, September 1, 2015 - link

    Add one more vote for the follow up with synthetics.
    I would also want to see how the multitasking compares with the Snapdragons as they use the different frequency and voltage planes per core instead of the big.LITTLE.
    But I guess that would be better to see with the SD 820, as the 810 uses big.LITTLE. Consider it a request for when it comes!
  • tuxRoller - Wednesday, September 2, 2015 - link

    Big.little can use multiple planes for either cluster. The issue is purely implementation, tmk.
  • TylerGrunter - Wednesday, September 2, 2015 - link

    big.LITTLE can be use different planes for each cluster but same for all cores in each cluster, Qualcomm SoCs can use different planes for each core, that's the difference and it's a big one.
    https://www.qualcomm.com/news/onq/2013/10/25/power...
    I'm not sure that can be done in big.LITTLE.
  • tuxRoller - Friday, September 4, 2015 - link

    I remember that but that doesn't say that big.LITTLE can't keep each core on its own power plane just that the implementations haven't.
  • soccerballtux - Tuesday, September 1, 2015 - link

    to balance everything out-- meh, that doesn't interest me. most of the time I'm concerned with battery life and every-day performance. Android isn't a huge gaming device so absolute performance doesn't interest me.
  • porphyr - Tuesday, September 1, 2015 - link

    Please do!
  • ppi - Tuesday, September 1, 2015 - link

    Go ahead. This is one of the most interesting performance digging on this site since the random-write speeds on SSDs.
  • jospoortvliet - Friday, September 4, 2015 - link

    Yes, this was an awesome and interesting read.

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