MIPS Strikes Back: 64-bit Warrior I6400 Arrives
by Stephen Barrett on September 2, 2014 10:00 AM ESTFinal Words
When it comes to processors, enthusiasts and laymen alike can identify the three largest players: Intel, AMD and ARM. Those names are also not mutually exclusive: AMD utilizes ARM designs for consumer security coprocessors and in its Opteron A1100 server processor. There are other processors out there (e.g. IBM's POWER CPUs), but they're generally not as well known. That's also the case with MIPS.
Not everyone knows the name MIPS, but Imagination hopes to change that by offering a viable alternative to the embedded market dominated by ARM. MIPS already has a large presence in networking and embedded devices. Introducing the I6400 keeps MIPS relevant and places additional pressure on ARM. According to the provided numbers (admittedly from MIPS) and feature descriptions, the I6400 appears to compete with and even surpass the highly anticipated ARM Cortex-A53. Imagination projects general availability of the I6400 to SoC designers by December 2014. We can estimate end-user availability at least 6 to 9 months after that.
Consumers will most likely directly experience the MIPS I6400 CPU in low cost Android tablets and handsets. Due to Android's Java heritage, some applications will work out-of-the-box. Other applications using the Android Native Development Kit (NDK) targeting Intel or ARM ISAs will unfortunately be incompatible. Until MIPS achieves enough volume to convince application developers to code to the MIPS3264 ISA or stick with Java, MIPS Android devices will be second class citizens. This is something to keep in mind if you're purchasing a phone for yourself or a tech savvy friend. Of course, basic operating system features like email, phone, text, web browsing, and chatting should all work fine.
Intel has enjoyed dominance of its performance leading processors in non-handset settings for the better part of a decade. ARMs embedded low power heritage has emerged as Intel’s biggest threat as mobile devices have exploded and now dominate the computing landscape. As Intel and ARM continue to battle for the high end embedded market, Imagination and MIPS hope to erode away ARM’s mid-range and low-end core competency. As a consumer, we can lean back and enjoy the competition that will force each company to work harder each and every year.
The I6400’s revised MIPS3264 Release 6 ISA, instruction bonding, and SMT execution pipeline bring a refreshing set of new innovations to the small-core market. In our A53 coverage we noted ARM was pushing in-order CPU performance about as far as it could possibly go. I’m always happy to see we might have been wrong.
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alexvoica - Wednesday, September 3, 2014 - link
CoreMark is a superior benchmark over DMIPS and reflects real world performance and workloads - not all, I agree but it still covers a lot more. If you look at our CoreMark results, you will notice we use gcc.https://www.eembc.org/coremark/
not proprietary (and expensive) compilers. I recommend you actually click on the link, see for yourself and then come back here and copy/paste what it says in the compiler section of that page.
Again, if you had read my article and the press release, you would have seen we actually have said that we lead in SPECint scores AND provide better performance when using multithreading.
I have no problem talking to you or anyone here trying to dispute our claims but let's keep it civilized and not imply I am deliberately lying.
bji - Wednesday, September 3, 2014 - link
Why are you so hostile? Calm the freak down man.Wilco1 - Tuesday, September 2, 2014 - link
SPEC has a multithreaded variant called SPECrate, this runs as many threads as you want. Various compilers (eg. icc) do autoparallelize some of the SPEC benchmarks even for the base results. This has made SPEC almost useless as a single-threaded comparison. So what people do is ignore Intel's icc results and rerun SPEC using GCC with identical options on the CPUs to be compared.Samus - Wednesday, September 3, 2014 - link
Wow name99 and Wilco1 chill the fuck out you're way over-complicating this article. When we have working devices we'll get the real benchmark comparisons to the "ARM equivalent" but its well understood MIPS has superior performance per watt capability at the cost of code and compiler complexity, in the same way ARM has superior performance per watt over x86 at the cost of x86 compatibility. The legacy P55C datapath inherently inflats the transistor count and inefficiency of x86 CPU's, and this is starting to become an issue for ARM as they have over 15 generations of designs, most of which are all backwards compatible with each other.MIPS has just 6 generations of designs to contend with, and was already a more efficient processing method from the get go. ARM's initially superior licensing model and incredibly successful development platform are what has lead to their success decades later.
Wilco1 - Wednesday, September 3, 2014 - link
When we have working devices we can compare performance per Watt. Until then which will be more efficient is just a guess. MIPS and ARM started around the same time and have similar baggage accumulated. Note MIPS is a simpler ISA and actually easier for the compiler as it doesn't have some of the more complex instructions that ARM has.Samus - Wednesday, September 3, 2014 - link
MIPSv6 is way more complex than ARM57, just like MIPSv1 was way more complex than ARM4JAVA is JAVA, but the compiler and instruction sets are more advanced in MIPS, hence more complex. An author may chose not to use a lot of extensions, but long story short, I work with programmers all the time and optimizing for MIPS is more work as optimizing for ARM. There are a lot of reasons for this (admittedly, industry support being one huge one.)
Wilco1 - Wednesday, September 3, 2014 - link
Cortex-A57 is ARM's highest performance and most complex OoO core. You can't compare that with MIPSv6 - an architecture. Wait until Imagination designs a CPU with comparable performance.MIPS is a simpler ISA than ARM, so compilers are easier to write. But MIPS pays for that by having to use more instructions to achieve the same task and more complex hardware to achieve the same performance. The fusing of 2 loads or stores is a very good example of this - if this was supported in the ISA like on ARM, it wouldn't need to be special cased. And while it improves performance, you still pay with larger codesize.
defiler99 - Thursday, September 4, 2014 - link
MIPS is hardly the "new kid on the block"; the MIPS instruction set has always been a rare example of beauty and simplicity in design.It's hardly fair to call that article "marketing fluff" either; have you seen some examples of true fluff? That isn't one.
puppies - Tuesday, September 2, 2014 - link
The time to admit your affiliation was before you started your first post, not after you got called out on it......alexvoica - Tuesday, September 2, 2014 - link
Called out for using my real name and claiming ownership (I, my) of the article from the first post? Don't think so.