Portal 2

A stalwart of the Source engine, Portal 2 is the big hit of 2011 following on from the original award-winning Portal.  In our testing suite, Portal 2 performance should be indicative of CS:GO performance to a certain extent.  Here we test Portal 2 at 1920x1080 with High/Very High graphical settings.

Portal 2 IGP, 1920x1080, Very High, 8xMSAA

Portal 2 mirrors previous testing, albeit our frame rate increases as a percentage are not that great – 1333 to 1600 is a 4.3% increase, but 1333 to 2400 is only an 8.8% increase.

Batman Arkham Asylum

Made in 2009, Batman:AA uses the Unreal Engine 3 to create what was called “the Most Critically Acclaimed Superhero Game Ever”, awarded in the Guinness World Record books with an average score of 91.67 from reviewers.  The game boasts several awards including a BAFTA.  Here we use the in-game benchmark while at the lowest specification settings without PhysX at 1920x1080.  Results are reported to the nearest FPS, and as such we take 4 runs and take the average value of the final three, as the first result is sometimes +33% more than normal.

Batman: AA IGP, 1920x1080, Ultra Low

Batman: AA represents some of the best increases of any application in our testing.  Jumps from 1333 C9 to 1600 C9 and 1866 C9 gives an 8% then another 7% boost, ending with a 21% increase in frame rates moving from 1333 C9 to 2400 C10.

Overall IGP Results

Taking all our IGP results gives us the following graph:

The only game that beats the MemTweakIt predictions is Batman: AA, but most games follow the similar shape of increases just scaled differently.  Bearing in mind the price differences between the kits, if IGP is your goal then either the 1600 C9 or 1866 C9 seem best in terms of bang-for-buck, but 2133 C9 will provide extra performance if the budget stretches that far.

Gaming Tests: Metro 2033, Civilization V, Dirt 3 Input/Output Testing
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  • nafhan - Thursday, October 18, 2012 - link

    "Random access" means that data can be accessed randomly as opposed to just sequentially. That's it. The term is a relic of an era where sequential storage was the norm.

    Hard drives and CD's are both random access devices, and they are both much faster on sequential reads. An example of sequential storage would be a tape backup drive.
    Reply
  • mmonnin03 - Thursday, October 18, 2012 - link

    RAM is direct access, no sequential or randomness about it. Access time is the same anywhere on the module.
    XX reads the same as

    X
    X

    Where X is a piece of data and they are laid out in columns/rows.
    Both are separate commands and incure the same latencies.
    Reply
  • extide - Thursday, October 18, 2012 - link

    No, you are wrong. Period. nafhan's post is correct. Reply
  • menting - Thursday, October 18, 2012 - link

    no, mmonnin03 is more correct.
    DRAM has the same latency (relatively speaking.. it's faster by a little for the bits closer to the address decoder) for anywhere in the memory, as defined by the tAA spec for reads. For writes it's not as easy to determine since it's internal, but can be guessed from the tRC spec.

    The only time that DRAM reads can be faster for consecutive reads, and considered "sequential" is if you open a row, and continue to read all the columns in that row before precharging, because the command would be Activate, Read, Read, Read .... Read, Precharge, whereas a "random access" will most likely be Activate, Read, Precharge most of the time.

    The article is misleading, using "sequential reads" in the article. There is really no "sequential", because depending if you are sequential in row, column, or bank, you get totally different results.
    Reply
  • jwilliams4200 - Thursday, October 18, 2012 - link

    I say mmonnin03 is precisely wrong when he claims that " no matter where the data is on the module the access time is the same".

    The read latency can vary by about a factor of 3 times whether the read is from an already open row, or whether the desired read comes from a different row than one already open.

    That makes a big difference in total read time, especially if you are reading all the bytes in a page.
    Reply
  • menting - Friday, October 19, 2012 - link

    no. he is correct.
    if every read has the conditions set up equally (ie the parameters are the same, only the address is not), then the access time is the same.

    so if address A is from a row that is already open, the time to read that address is the same as address B, if B from a row that is already open

    you cannot have a valid comparison if you don't keep the conditions the same between 2 addresses. It's almost like saying the latency is different between 2 reads because they were measured at different PVT corners.
    Reply
  • jwilliams4200 - Friday, October 19, 2012 - link

    You are also incorrect, as well as highly misleading to anyone who cares about practical matters regarding DRAM latencies.

    Reasonable people are interested in, for example, the fact that reading all the bytes on a DRAM page takes significantly less time than reading the same number of bytes from random locations distributed throughout the DRAM module.

    Reasonable people can easily understand someone calling that difference sequential and random read speeds.

    Your argument is equivalent to saying that no, you did not shoot the guy, the gun shot him, and you are innocent. No reasonable person cares about such specious reasoning.
    Reply
  • hsir - Friday, October 26, 2012 - link

    jwilliams4200 is absolutely right.

    People who care about practical memory performance worry about the inherent non-uniformity in DRAM access latencies and the factors that prevent efficient DRAM bandwidth utilization. In other words, just row-cycle time (tRC) and the pin bandwidth numbers are not even remotely sufficient to speculate how your DRAM system will perform.

    DRAM access latencies are also significantly impacted by the memory controller's scheduling policy - i.e. how it prioritizes one DRAM request over another. Row-hit maximization policies, write-draining parameters and access type (if this is a cpu/gpu/dma request) will all affect latencies and DRAM bandwidth utilization. So just sweeping everything under the carpet by saying that every access to DRAM takes the same amount of time is, well, just not right.
    Reply
  • nafhan - Friday, October 19, 2012 - link

    I was specifically responding to your incorrect definition of "random access". Randomness doesn't guarantee timing; it just means you can get to it out of order. Reply
  • jwilliams4200 - Friday, October 19, 2012 - link

    And yet, by any practical definition, you are incorrect and the author is correct.

    For example, if you read (from RAM) 1GiB of data in sequential order of memory addresses, it will be significantly faster than if you read 1GiB of data, one byte at a time, from randomly selected memory addresses. The latter will usually take two to four times as long (or worse).

    It is not unreasonable to refer to that as the difference between sequential and random reads.

    Your argument reminds me of the little boy who, chastised by his mother for pulling the cat's tail, whined, "I didn't pull the cat's tail, I just held it and the cat pulled."
    Reply

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