The Bulldozer Aftermath: Delving Even Deeper
by Johan De Gelas on May 30, 2012 1:15 AM ESTBranch Prediction Analysis
The AMD engineers overhauled the branch prediction unit(s) completely in Bulldozer. Did they succeed in closing the gap with Intel, which has had superior branch prediction for years now ? Let us see.
The new Opteron's BPU performs at least as good and sometimes significantly better than old one. This is another component that AMD really got right. However, Intel's BPU clearly wins in SQL Server.
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Aone - Monday, June 4, 2012 - link
Bulldozer's conception was wrong from the scratch.I told it a few time, let's me explain it here again.
I'm sure everyone of you do remember AMD's own words "one BD module has 80% of throughput of two independent cores".
What does this mean in figures?
Let's take the performance of one core as 1.0 point. Therefore two BD modules would have 3.2 points or in other words less than 10% than 3.0 (performance of three independent cores).
Should I remind that with development of independent cores AMD wouldn't had wasted resources (engineering, transistors, money and time) on design and debugging the shared logic. The chip could have been much smaller due to the fact that the chip would have had only 1MB L2 and 2MB L3 per each core and no shared logic. And all of those released resources could have been allocated for development of a more advanced core.
You see that packing two cores inside a one module was wrong even on the conceptional level. I'm very curious who was the main supporter and decision maker of this approach in AMD.
AMD must through away BD conception and return to standard practice. The only question remains: Does AMD have long enough TTL to do it?
BTW, I recommend to look through Spec results again. The comparison of 12c Opteron 62xx w/ 12c Opteron 61xx is of special interest. And let's not forget that Opteron 62xx submissions have higher freq, faster memory and as well as more advanced compiler version and extended instruction set.
TC2 - Monday, June 18, 2012 - link
I'm agree in 100%!!!The BD uA is "unsuccessful" port from graphics uA. There is many and major drawbacks! Note for example one - to write an optimal software you must adopt an application at algorithmic level (in sense of thread specialization)! This is because the both BD-cores are not the same! Also they shares L1 IC, the number of elements is high, ... and many others uA weaknesses.
evolucion8 - Tuesday, June 17, 2014 - link
Northwood was 20 stage pipelines and Prescott was 31, not 39...tipoo - Wednesday, October 8, 2014 - link
Where is the aftermath?"But what about the fourth show stopper? That is probably one of the most interesting ones because it seems to show up (in a lesser degree) in Sandy Bridge too. However, we're not quite ready with our final investigations into this area, so you'll have to wait a bit longer. To be continued...."