Intel Celeron 600 "Coppermine128"

FSB - 66MHz vs 100MHz

Since all Celerons have locked clock multipliers, it is impossible to run a Celeron 600 at 66MHz x 9.0 and 100MHz x 6.0 to test the effects of the 100MHz FSB in addition to the 100MHz memory bus on performance.

Luckily, since the new Celeron only differs from the Pentium III in that it features 128KB of L2 cache instead of the 256KB on Pentium III, by disabling the L2 cache on the Celeron and on the Pentium III we can put together a pretty nice match-up to compare the effects of the 100MHz FSB on the Celeron in order to find out if this is a limitation of the design.

We used the same VIA 133A platform from before so that we could adjust the memory bus frequency in addition to the FSB frequency and the L2 cache was left disabled in order to level the playing field. Disabling the L2 cache also makes the system more memory dependent because the CPU has no level 2 cache to go to for data and thus must go directly to system memory. While this does somewhat exaggerate the effects of the memory bus on performance it is necessary in order to illustrate the point.

We already found out that going to a 100MHz memory bus would give us a small performance improvement under CC Winstone 2000 from the earlier tests but by increasing the FSB to 100MHz as well the performance improvement more than doubles offering a 16% improvement over the 600/66MHz clock of the Celeron 600.

Although the Pentium III 600E has a 128KB L2 cache advantage over the Celeron 600 most of its performance improvement should come from the 100MHz FSB and 100MHz memory bus rather than the larger L2 cache.

Under SYSMark 2000 approximately 11% of the 26% improvement in performance is due to the 100MHz memory bus, the remaining 15% is due to the increased FSB frequency.