The Good & Bad of IA-64

As a member of the IA-64 family, the Itanium is obviously geared towards 64-bit application performance that is optimized for the processor’s technology. Unfortunately for the Itanium, most of the applications available at the release of the CPU later this year will still be for the IA-32 family. This brings up the most prevalent concern about the Itanium, its IA-32 performance. The Itanium will most likely be inferior to the Willamette in terms of IA-32 performance, which effects more users that those that would benefit immediately from the IA-64 support of the CPU.

As the transition from IA-32 to IA-64 takes place, the focus on the Itanium’s IA-32 performance will obviously decrease, however until the move to IA-64 technology as a standard is complete, at least for workstations and servers that don’t require the benefits of IA-64 and/or don’t feature IA-64 compliant applications, the Itanium won’t be an overly accepted platform.

One of the major benefits of the Itanium, courtesy of its 64-bit architecture, is the 64-bit memory addressing capabilities. Being able to address massive amounts of system memory is a demand that has been made by the larger online entities such as the search engines and e-commerce sites. But for the normal desktop or workstation user, being able to use 30GB of memory isn’t a major concern.

The integer performance of the Itanium is supposed to be "competitive" with the Willamette but the major performance benefits of the Itanium come from its powerful FPU. In the high-end workstation market, a powerful FPU is definitely a desired feature and the Itanium is designed to offer just that.

The Itanium as a processor will feature a fairly large Level 3 cache which gives it another benefit over the current generation of high end processors from Intel. If you look at the server market for example, most users are refraining to upgrade their 1MB Xeons to the new 800MHz Xeons simply because they have 1/4 of the L2 cache. The cache size of the Itanium should be a very attractive feature to most users that experienced a performance benefit courtesy of the Xeons with larger L2 caches.

Index The Chip

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