First Results



First up are the maximum stable FSB shots. These come in at 2V on the memory and around 1.67 VMCH. That's probably too high for the conservative overclockers among us, not to mention these settings favor a water-cooled Northbridge. In testing, 555FSB is absolutely stable, performance is okay, but we had to set "Enhanced Data Transmitting" to disabled in the DFI BIOS.

Read bandwidth in our Everest test is just over 11K here as is write speed. Copy bandwidth suffers because of the disabled performance registers, posting a mere 9K or so. The numbers are respectable enough, and the DFI board can certainly run two 3870s in CrossFire mode at a somewhat high FSB speed. Let's push for a better performance ratio.



We usually prefer running our PCs where they perform best, and typically for the X48 chipset this performance zone falls at a tRD of 6 with the FSB speed at around 460-470. Although, the downside of running a lower FSB does manifest itself with lower overall copy and write speeds, so we sometimes settle for a tRD of 7 at 500FSB. In this instance, the stock specification of these modules demands 533FSB and that means a looser tRD of 8 on all X48 boards.

Now comes the reason behind the perceived synergy of the parts we are using together. Usually, running the 2:1 memory divider on the X48 chipset over 510FSB requires a lot of the chipset performance registers to be set low. The DFI board has a bit of an advantage here over other boards; it can run and hold these performance enhancements steady at 533 FSB. The result is spectacular bandwidth right across the spectrum, while access latency is also no slouch.

Voltage-wise, the MCH demands between 1.6V and 1.65V to remain stable with these loads. Again we find ourselves using fans that provide a copious amount of noisy airflow or a decent water loop to keep the Northbridge cool for a 24/7 system running these speeds (and even with such cooling, we're far more inclined to drop the speeds a bit). Of course, it's possible to loosen tRD to bring the VMCH down, but the logic in doing so does not sit well with the decision to purchase a CAS 9 2133MHz memory kit.



Yes, our settings are fully stable, but the motherboard still exhibits a tendency to sit staring back at us with a code 88 displayed in the POST code display when we cold boot the system. Simply reloading the BIOS gets around it, so it's just a matter of tidying up the BIOS by DFI to rectify our problem. A complete BIOS guide will follow shortly as part of the full board/memory review. The story for now is that yes, DDR3-2133 speeds or higher can be done for a 24/7 system, but be prepared for a few days of tuning and hair pulling. It's just not that easy yet.

Reaching DDR3-2133, the hard way
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  • hoohoo - Wednesday, September 10, 2008 - link

    I want bandwidth numbers!
  • geok1ng - Thursday, August 28, 2008 - link

    It would be good to see a table with CAS, Trd, dividers and frequencies for DDR3 users, just as you did for DDR2 users on the Rampage formula review http://www.anandtech.com/mb/showdoc.aspx?i=3208&am...">http://www.anandtech.com/mb/showdoc.aspx?i=3208&am...

    using the data from these tables i would infer that the best option for an E8600 and a high end DDR3 is:
    2:1 divider
    tRD of 5
    CPU at 10x400
    DDR3 1600
    These are the highest 12,5ns Trd timings displayed. Are they valid for a X48 DDR3 mobo?
    If they are possible at CAS 6, just how far can the FSB be increased while keeping the tRD at 5?
    What DDR3 modules are capable of reaching DDR3 1600+ at CAS 6 with the least voltage?

    on the Rampage review the authors proposed a DDR2 1000 CAS 4 solution as the best option for running four sticks of RAM, with DDR2 1200 CAS 5 as an alternative for 2 sticks of RAM.

    What are Anandtech suggestions for DDR3 builds on the X48 chipset?
  • Berger - Thursday, August 28, 2008 - link

    Aiming for a tRD of 6 at around 450FSB on the 2:1 divider brings the best overall balance for a 24/7 system. tRD 5 is attractive but you will lose out on copy and write bandwidth without sufficient FSB to bolster bandwidth. Plus the VMCH requirement is rather high for outright stability.

    For quad processors sticking around 400FSB is the best option, tRD 5 is likely to be too tight for some boards when armed with 4GB of memory.

    Personally I don't like suing 'down' dividers - ie anything that pits the FSB slower than the memory bus. Too many wasted clock cycles.

    regards
    Raja


  • geok1ng - Sunday, August 31, 2008 - link

    So the problem is that for 10x450-a typical result for an E8600 at 1,4v- one can either run the memory at 2:1 and relaxed tRD and CAS or try slower memo speeds but tighter CAS and tRD. quoting the article i posted:
    "Moving on to the analysis at 450Mhz FSB, although we are able to show impressive memory read speeds at this same bus frequency using a 3:2 divider for DDR2-1350 CAS 5 at a tRD of 5, this configuration was far from stable on stock cooling alone - as was the memory speed. Most likely, the need to loosen tRD to 6 will be inevitable at this bus speed"

    So from your tests DDR3 based mobos didnt break the 1350Mhz barrier for tRD 5 operation?

    Is CAS 5,tRD 5 at the 1250-1350 range really that demanding on the NB?

    Is CAS 6,tRD 6 at 1800Mhz so much faster?

    What about CAS 5 tRD 6 operation at DDR3 1710 as in http://www.xtremesystems.org/FORUMS/showthread.php...">http://www.xtremesystems.org/FORUMS/showthread.php... Sure the write and copy speeds are lower, but 45ns latency at "just" 1710Mhz is nothing to be ashamed of.
  • Berger - Thursday, August 28, 2008 - link

    *Edit* that should read using down dividers where the memory bus is running slower than the FSB. We don't have up didviders on DDR3 anyway. 2:1 is where the action is at on DDR3.

    regards
    Raja
  • strikeback03 - Thursday, August 28, 2008 - link

    You sign as Raja here, as Berger in the NVIDIA comments, who are you?
  • nevbie - Thursday, August 28, 2008 - link

    Putting those BIOS screens into a gallery looks good - it's the first time I see this new gallery function used in an interesting way.

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