Intel's Core Duo Launch - Notebook Performance Revealedby Anand Lal Shimpi on January 5, 2006 8:00 PM EST
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Napa vs. Sonoma - Tangible Features
While the most exciting element of today’s launch is Intel’s Core Duo microprocessor, there are some other benefits that Napa provides us with over Sonoma. As far as we can tell, the majority of the tangible non-CPU performance improvements are actually contained within the Intel 945 Express chipset.
Napa bumps up the FSB frequency from 533MHz in Sonoma to 667MHz, giving the Core Duo a 25% increase in FSB bandwidth over its predecessor. Given that there are now two cores being fed by the same FSB, an increase in FSB bandwidth is necessary and appreciated. However unlike on desktop platforms, Intel can’t just increase FSB frequency like mad simply because higher bus frequencies mean greater power consumption, or lower battery life. Napa could have probably benefitted from a faster FSB, but the upgrade will probably have to wait until a later date.
Along with a faster FSB, the 945 Express chipset brings DDR2-667 support to the table. We have seen manufacturers continue to use DDR2-533 as well as shift over to DDR2-667, so just because the support is there don’t expect everyone to take advantage of it. The truth of the matter is that even with DDR2-533, since the platform is dual channel, there is already enough memory bandwidth to feed the 667MHz FSB. The only thing DDR2-667 brings to the table is better performance for integrated graphics and lower latency memory accesses as it runs synchronous with the 667MHz Napa FSB.
Other than the faster FSB and memory bus, Napa’s remaining features outside of the Core Duo processor are predominantly power related.
A Lower Power Chipset
One claim that Intel has been making for quite some time is that Centrino Duo will offer better performance at lower power consumption than the previous generation Centrino platforms. While we will investigate that claim with performance and battery life tests later on in this article, it’s important to look at the building blocks that would support such a claim.
As we found with the original Centrino platform, reducing the power consumption of the CPU is only part of the equation. The FSB, chipset and wireless controller all contribute to power consumption in the system and they all have to be addressed individually in order to truly increase battery life on notebooks.
The FSB issue was originally addressed with the first Centrino platform, which ensured that the IO buffers on the FSB interface were initially in an off state until eventually woken up before data could be sent over the bus. The downside to this approach was that there was an additional latency penalty incurred while waiting for the buffers to wake up, but the benefits were reduced overall power consumption.
The chipset and wireless solutions have both been undergoing reductions in power consumption over the past couple of years. Most recently, the Sonoma platform used in the last generation Centrino offered lower power consumption than the original platform, and of course Intel is promising the same today with the Napa platform used in Centrino Duo notebooks.
The 945 Express chipset is still built on a 130nm process (just like the 915 used in Sonoma), but promises lower power consumption for two basic reasons. The ICH7M used in the 945 Express chipset is a lower voltage redesign of ICH6 used in Sonoma. A lower voltage design itself may not necessarily reduce power consumption, but the new ICH also incorporates more aggressive clock gating (turning off the clock supplied to various blocks of the ICH when not in use) and IO buffer gating (turning off the IO buffers when not in use) to achieve lower power usage.
The second force at play to reduce the chipset’s power consumption is what Intel is referring to as “aggressive design enhancements” on PCIe blocks. Intel couldn’t go into detail here but we’re guessing that they are talking about slight design changes to reduce power consumption in their PCIe controllers on the chipset. The impact of these changes won’t be huge, but it should contribute to an overall reduction in power. Once again, although not going into great detail, Intel did mention that they were able to reduce power in many of their analog circuits as well - most likely through careful investigation and redesign of power hungry elements of the chipset.
We have heard of overall power reductions of as much as 3W thanks to the chipset optimizations mentioned here. While it’s difficult to isolate just the chipset and measure the power consumption ourselves, at least we can be somewhat confident that there is no increase in power consumption of the new platform. Later this year, Intel will migrate their chipsets down to 90nm which should allow for even greater reductions in power consumption.