Today in London as part of ARM's TechDay 2015 event we had the pleasure to get a better insight into ARM's new Cortex-A72 CPU. ARM had announced the Cortex-A72 in the beginning of February - leaving a lot of questions to be asked and sense of mystery in the air. The Cortex-A72 is a direct successor to the Cortex-A57 - taking the predecessor as a baseline in order to iterate and improve it.

On the naming side of the equation, moving from 'A57' to 'A72' rather than 'A59' or similar, ARM explains that it is purely a marketing decision as they wanted to give better differentiation between its higher-performance cores from the mid-tier and low-power cores. There seemed to be some confusion between the more power efficienct A53 and the more powerful A57, whereby users would assume they are similar, and thus moving its new big core into the A7x series.

We saw some absolute targeted performance numbers back during the February release, which promised some very interesting numbers that could be achieved over the A57. The problem was that it was not clear how much from performance and power efficiency came from the architectural changes and how much came from the the process on which these targeted performance data points are estimated from. It's clear that on the high-end ARM is promoting the A72 on the new FinFET processes from Samsung/GlobalFoundries and TSMC, which are referred to as 14nm and 16nm in the slides. Generally, due to the design and the node, the A72 will be able to achieve higher clocks than the A57, and we seem to be aiming around 2.5GHz on the 14/16nm nodes when high-end smartphones are concerned. Higher clocks may be present in server applications, where the A72 is also aimed at.

Probably the most interesting slide next to the actual performance metrics of the A72 is the apples-to-apples comparison of the A57 to the A72 on the same process node. When on the 28nm node, we see the A72 having a respectable 20% power reduction when compared to the A57. As a reminder - we're talking about absolute power at the same clock speed, which does not consider performance and thus not a representation of efficiency.

Notably, ARM is aiming for the A72 to be capable of extensive sustained performance at its target frequency. This is something that smaller form factor A57 designs (e.g. phones) have struggled with due to just how powerful A57 is, which has lead to more bursty designs that can only run A57 at its top speeds for short periods of time. We are presented with figures such as sustained 750mW operation per core on 16FF+ at clocks of ~2.5GHz.

While the power numbers are interesting we also have to put them into context of the achieved work. ARM has made several optimizations to the architecture to improve performance when compared to the A57. We'll get into more detail in just a bit - but what we are looking at is a general 16-30% increase on IPC depending on the kind of workload. Together with the power reduction, we now see how ARM is able to advertise such large efficiency gains for the same fixed workload.

A72 Architecture - The Upgrades Over A57

ARM seems to have managed to achieve an improvement in all three areas of the PPA metric; Performance, Power and Area - the trifecta of semiconductor design goals. This was achieved by doing a re-optimization of (almost) every logical block from the A57. There has been some considerable redesign in the CPU's architecture, some of which include a new branch-predictor and improvements in the decoder pipeline to allows for better throughoutput. 

On the level of the instruction fetch block we see a brand new branch-predictor that follows a new sophisticated algorithm that improves performance and reduces power through reduced misprediction and speculation, which has been cut down by 50% for mispredictions and 25% for speculation when compared to the A57. Superfluous branch-predictor accesses have also been suppressed - in workloads where the predictor is not able to do its job efficienctly it is then bypassed completely. There also has been general power optimization in the RAM-organization by coupling the different IP blocks better together, something ARM looks to provide with their own physical IP.

Moving down the pipeline, A72's decoder/rename capabilities have seen their own set of improvements.The decoder itself is still a 3-wide decoder, but ARM has gone through it to try to improve both performance and power consumption in other ways. To improve performance, the effective decode bandwidth has been increased, and the decoder has received some AArch64 instruction-fusion enhancements. Meanwhile power consumption has been tempered at multiple levels, including optimizing decoding directly, and in other power optimizations to the buffers and flow-control hardware that work around the decoder.

However it's on the dispatch/retire stage that the architecture sees the biggest improvements to performance. Going hand-in-hand with the decoder's ability to fuse instructions, ARM's dispatch unit can then break those ops back down into more granular micro-ops for feeding into the execution units, transforming it from a 3-wide to an effective 5-wide machine at the dispatch stage. The net result of this increases decoder throughput (by reducing the number of individual instructions decoded) while also increasing the total number of micro-ops created by the dispatcher and eventually executed per cycle. ARM is quoting an average of 1.08 micro-ops per instruction in code, which will aid the cases where in A57 the 3-wide dispatch unit was eventually dispatch limited. Again on the dispatch-level, ARM has done more extensive work on their register file by reducing the number of read-ports by introducting port-sharing and further reducing superfluous access.

ARM CPU Core Comparison
  Cortex-A15 Cortex-A57 Cortex-A72
ARM ISA ARMv7 (32-bit) ARMv8 (32/64-bit)
Decoder Width 3 ops
Maximum Pipeline Length 19 stages 16 stages
Integer Pipeline Length 14 stages
Branch Mispredict Penalty 15 cycles
Integer Add 2
Integer Mul 1
Load/Store Units 1 + 1 (Dedicated L/S)
Branch Units 1
FP/NEON ALUs 2x64-bit 2x128-bit
L1 Cache 32KB I$ + 32KB D$ 48KB I$ + 32KB D$
L2 Cache 512KB - 4MB 512KB - 2MB 512KB - 4MB
 

On the side of the execution units we see introduction of new, next-generation FP/Advanced SIMD units. The new units allow for much lower instruction latency as the FP pipeline length is reduced from 9 to 6.  FMUL is reduced from 5 cycles down to 3, FADD goes from 4 to 3, FMAC from 9 to 6, and the CVT units go from 4 to 2 units. The reduction of the FP pipeline length brings down the maximum pileline length of the architecture down from 19 to 16. 

The integer units also see an improvement, as the Radix-16 divider has seen its bandwidth doubled, while the CRC unit now becomes a pipelined block with just 1-cycle latency, a 3x increase in bandwidth over the A57. Again, we see a repeating pattern here as ARM claims it tried to squeeze the most power efficiency from all the units by improving the physical implementation.

Another large performance improvement over the A57 is found on the Load/Store unit. Here, ARM claims that bandwidth to L1/L2 has been improved by up to 30%. This was achieved by introducting a sophisticated L1/L2 data prefetcher which, again, is at the same time more efficient as improvements in the L1-hit pipeline, fowarding network, and way-predictor reduce the needed power. 

We've been generally impressed with what the A72 brings to the table. It's clear that new architecture is an evolutional upgrade ot the A57, and the improvements in performance, power, and area, when looked at from an aggregate view, bring substantial differences and upgrades when compared to the A57. With the A57 having come to market in Q3 of last year and it now shipping in high-volume SoCs such as the Snapdragon 810 and Exynos 7420, we are looking at the possibility of seeing its successor come to market in shipping devices in less than a year's time. The obvious partners that might ramp prodution the soonest are MediaTek and Qualcomm, at least if they are able to hit their target schedules. There should presumably still be un-announced parts from other ARM partners as well. It's clear that ARM has increased the cadence of releasing refreshes of its IP portfolio and the quick succession of the A72 seems to be part of that.

The A72 looks to be a logical update to the A57 addressing some weakpoints such as peak power and power efficiency combined with an ~10% area reduction. We already saw Mediatek showing off an A72 package at MWC, so it will be interesting to see how the IP actually performs in silicon and what ARM's partners will be able to do with the core and the time to market.

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  • Ryan Smith - Friday, April 24, 2015 - link

    It's like an optimization, but it's optional. Reply
  • LukaP - Friday, April 24, 2015 - link

    Interesting. I need to write this one down... Reply
  • Drumsticks - Friday, April 24, 2015 - link

    No thoughts on the ambitious goal/stated intention of using 75% of the power of broadwell for similar performance? Arstechnica indicated that ARM felt VERY confident in that claim. Reply
  • iwod - Friday, April 24, 2015 - link

    I am interested in how it compares to 14nm Intel Atom Core.
    I am going to assume Intel still has the edge on performance? Or has that finally been closed down with A72?
    Reply
  • iwod - Friday, April 24, 2015 - link

    I am interested in how it compares to 14nm Intel Atom Core.
    I am going to assume Intel still has the edge on performance? Or has that finally been closed down with A72?

    Edit: Turns out that Ars has a slide that said A72 is 75% within Broadwell, truly impressive.
    Reply
  • jjj - Friday, April 24, 2015 - link

    Atom has never had the edge on perf and the 14nm Atom is just a die shrink without higher clocks so A72 obliterates it but to be fair i have no idea how big the Atom core is on 14nm and we are yet to be certain that A72 hits it's power targets.
    As for the Broadwell slide it seems to be Broadwell at 2GHz vs A72 at 2.5GHz and the under 1W vs 4W is a bit misleading. Doubt a single core will use all those 4W.
    http://cdn.arstechnica.net/wp-content/uploads/2015...
    In multi core 4 ARM cores would be at 3W(4x750mW) vs Intel at 4W with dual core /4 threads and the cores would fail to reach the max 2GHz because of the 4W limitation.
    Single core vs single core A72 at 2.5GHz might match Broadwell at 2GHz in integer and memory but not in FP, at least that seems to be the case in Geekbench.
    Those benchmarks in the slide are not fake, they are just slightly creative so you have to avoid the traps. Also ARM doesn't actually have the silicon for A72.
    In 4 cores vs 2 cores and likely even 2 cores vs 2 cores at the tested speeds, A72 beats it when Broadwell is limited to such low power.
    Ofc Broadwell is not designed for low clocks and low power and it's a hell of a lot bigger so it's not all that impressive in this kind of scenario.
    A72 expected perf is very exciting and things will get more interesting.
    A few days ago a slide leaked with future ARM cores and it seems they will have a core called Ares on 10nm targeting 1 to 1.25W while A72 is targeted at 0.75W. A 66% increase in power and a new process should mean big perf gains.
    Reply
  • Speedfriend - Friday, April 24, 2015 - link

    @jjj
    Even with the usual grain of salt when looking at comparatives that ARM slide is really pushing it.

    It is comparing the lowest Spec Broadwell 5Y10 which has a geekbench single core score 40% lower than the top spec 5Y71.

    As there is no single core broadwell and there certainly won't be a single core A72, comparing the full power consumption of Broadwell at 4W against A72 at 1W is just plain lying.

    They are making the assumption that the Core M will be thermally limited and not achieve full target frequency, when Anandtech results have shown that it is highly dependent on the work load and form factor.

    It is comparing a theoretical design potentially available early next year, with a shipping chip already available for 6 months and which will have already been replaced by a chip likely to have 20% better performance.

    I now know why the guys at Imagination tend to be highly sceptical of anything that Arm claims.
    Reply
  • psychobriggsy - Friday, April 24, 2015 - link

    In the end the slide is making the point that the A72 achieves similar results in a lower power budget than the Core M, whether it's a single core or multiple cores. When the chassis cooling is good, then Core M can turbo beyond its TDP for longer, so is it still 4W? How would A72 perform if allowed to run at a higher TDP?

    In addition, SoCs using A72 are going to be priced in the $40 range at most, possibly down to $20. Core M is in a different ballpark in this regard.

    However Core M is available now, whereas the first A72s will be late this year at best.
    Reply
  • jjj - Friday, April 24, 2015 - link

    My estimates for Geekbench were based on existing results for the MT8173 and those are in line with what i said and what ARM said.Plus i did my part in trying to explain how ARM is being "creative"
    Ofc while we have some early perf numbers for a dev board ,we don't have any real world power numbers.
    I will also point out that he quoted price for Core M is 281$ while dual A72+dual A7 tablet SoCs will likely be as low as 10$.
    Amazon is using 2xA15+2xA7 from Mediatek in it's cheaper tabs and this dual A72 is replacing that so soon enough we might see it in some 100-150$ Kindle.
    Reply
  • V900 - Friday, April 24, 2015 - link

    You do realize that there isn't any reason beyond appetite for profit margin, that Intel charges 280$ for a Broadwell CPU, right?

    Now IF ARMs theoretical design comes out in a year, and will offer close to the same performance as Intel's slowest Broadwell processor that came out six months ago, there's nothing that prevents Intel from smacking an Atom label on them, and sell them for 40$ or 20$.

    (Actually that's probably what they'll do, since Intel will have a much faster Skylake or Cannonlake CPU out by then to charge 200-400$ for...)

    Why do people often treat ARM like some chubby kid with Down's syndrome who's competing at a track meet because nobody wanted to tell him he didn't make the cut?!?

    "Oh wow, look at that ARM-kid! He's almost as fast as the Intel runner! GOOD JOB ARM!! WHOOO YOU ROCK!! You know, he could actually win this if he had a 1 lap head start!"
    Reply

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