TSX

Johan did a great job explaining Haswell's Transactional Synchronization eXtensions (TSX), so I won't go into as much depth here. The basic premise is simple, although the implementation is quite complex.

It's easy to demand well threaded applications from software vendors, but actually implementing code that scales well across unlimited threads isn't easy. Parallelizing truly independent tasks is the low hanging fruit, but it's the tasks that all access the same data structure that can create problems. With multiple cores accessing the same data structure, running independent of one another, there's the risk of two different cores writing to the same part of the same structure. Only one set of data can be right, but dealing with this concurrent access problem can get hairy.

The simplest way to deal with it is simply to lock the entire data structure as soon as one core starts accessing it and only allow that one core write access until it's done. Other cores are given access to the data structure, but serially, not in parallel to avoid any data integrity issues.

This is by far the easiest way to deal with the problem of multiple threads accessing the same data structure, however it also prevents any performance scaling across multiple threads/cores. As focused as Intel is on increasing single threaded performance, a lot of die area goes wasted if applications don't scale well with more cores.

Software developers can instead choose to implement more fine grained locking of data structures, however doing so obviously increases the complexity of their code.

Haswell's TSX instructions allow the developer to shift much of the complexity of managing locks to the CPU. Using the new Hardware Lock Elision and its XAQUIRE/XRELEASE instructions, Haswell developers can mark a section of code for transactional execution. Haswell will then execute the code as if no hardware locks were in place and if it completes without issues the CPU will commit all writes to memory and enjoy the performance benefits. If two or more threads attempt to write to the same area in memory, the process is aborted and code re-executed traditionally with locks. The XAQUIRE/XRELEASE instructions decode to no-ops on earlier architectures so backwards compatibility isn't a problem.

Like most new instructions, it's going to take a while for Haswell's TSX to take off as we'll need to see significant adoption of Haswell platforms as well as developers embracing the new instructions. TSX does stand to show improvements in performance anywhere from client to server performance if implemented however, this is definitely one to watch for and be excited about.

Haswell also continues improvements in virtualization performance, including big decreases to guest/host transition times.

Decoupled L3 Cache Haswell's GPU
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  • FunBunny2 - Tuesday, October 09, 2012 - link

    If Steve hadn't done what Apple does best (according to Steve) "steal" BSD unix, would you still be crowing? Reply
  • Magik_Breezy - Sunday, October 14, 2012 - link

    His operating system doesn't crash 7 times a day because he doesn't run OS X, I'll rephrase that, because he isn't a retard Reply
  • HisDivineOrder - Sunday, October 07, 2012 - link

    Let's not forget the obscenely high failure rates due of Macbook Pro's because they are huge, metallic, and yet refuse to have vents ruin the smooth awesomeness of their aesthetic.

    Whoops, for many it won't last more than two years, if that. Hell, if you're lucky, your battery will give out before your laptop cooks. Regardless, look up what Apple suggests and you'll get:

    Buy another one. Yours is old. ;)
    Reply
  • Magik_Breezy - Sunday, October 14, 2012 - link

    Anything delivers "solid performance" on Facebook & iWork
    Why pay $2,000 for that?
    Reply
  • random2 - Friday, October 05, 2012 - link

    I agree. admittedly I am not an apple fan and view them as people who have undergone a degree of brainwashing compounded by the need for some to keep up with the Jone's. A certain degree of mind control must be necessary to stick with a company that has had some questionable business practices as far as customer relations, dealing with product issues and denying said issues, not to mention the whole hypocritical stance by apple in regards to copyright infringement has also left a bad taste in my mouth. Reply
  • hasseb64 - Saturday, October 06, 2012 - link

    Disagree, not that much new from already published IDF reports almost 1 month ago. What is intresting is the claimed 40 EU GT3, other sources say lower amounts. Reply
  • JKflipflop98 - Saturday, October 06, 2012 - link

    I totally agree. It's articles like this that have kept me coming back for years. Keep up the good work Anand! Reply
  • tipoo - Sunday, October 07, 2012 - link

    "You can expect CPU performance to increase by around 5 - 15% at the same clock speed as Ivy Bridge. "

    That seems terribly disappointing for a tock, even IVB as a Tick managed 10% in most cases.
    Reply
  • medi01 - Tuesday, October 09, 2012 - link

    One can't be biased !@# !@#@ and a good journalist at the same time.
    One needs to be blind not to see how glass is always half empty for AMD, and half full for nVidia/Intel. F**!@#'s were shameless enough, to test 45W APU with 1000W PSU and such crap is all over the place.
    Reply
  • Paulman - Friday, October 05, 2012 - link

    As I was reading this article, about part way into the low platform power sections I suddenly had this thought: "Oh man, AMD is gonna die...!"

    I don't know if that's true for the entire microprocessor side of AMD, since they look like they're already starting to transition out of the desktop space, but I don't know if they're going to stand much of a chance if they're planning on entering the same TDP range as Haswell.

    Do you think there's a chance AMD will start focussing on designing ARM ISA cores? Or will expanding on their x86 Bobcat-type cores be enough for them?
    Reply

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