The Haswell Front End

Conroe was a very wide machine. It brought us the first 4-wide front end of any x86 micro-architecture, meaning it could fetch and decode up to 4 instructions in parallel. We've seen improvements to the front end since Conroe, but the overall machine width hasn't changed - even with Haswell.

Haswell leaves the overall pipeline untouched. It's still the same 14 - 19 stage pipeline that we saw with Sandy Bridge depending on whether or not the instruction is found in the uop cache (which happens around 80% of the time). L1/L2 cache latencies are unchanged as well. Since Nehalem, Intel's Core micro-architectures have supported execution of two instruction threads per core to improve execution hardware utilization. Haswell also supports 2-way SMT/Hyper Threading.

The front end remains 4-wide, although Haswell features a better branch predictor and hardware prefetcher so we'll see better efficiency. Since the pipeline depth hasn't increased but overall branch prediction accuracy is up we'll see a positive impact on overall IPC (instructions executed per clock). Haswell is also more aggressive on the speculative memory access side.

The image below is a crude representation I put together of the Haswell front end compared to the two previous tocks. If you click the buttons below you'll toggle between Haswell, Sandy Bridge and Nehalem diagrams, with major changes highlighted.


In short, there aren't many major, high-level changes to see here. Instructions are fetched at the top, sent through a bunch of steps before getting to the decoders where they're converted from macro-ops (x86 instructions) to an internally understood format known to Intel as micro-ops (or µops). The instruction fetcher can grab 4 - 5 x86 instructions at a time, and the decoders can output up to 4 micro-ops per clock.

Sandy Bridge introduced the 1.5K µop cache that caches decoded micro-ops. When future instruction fetch requests are made, if the instructions are contained within the µop cache everything north of the cache is powered down and the instructions are serviced from the µop cache. The decode stages are very power hungry so being able to skip them is a boon to power efficiency. There are also performance benefits as well. A hit in the µop cache reduces the effective integer pipeline to 14 stages, the same length as it was in Conroe in 2006. Haswell retains all of these benefits. Even the µop cache size remains unchanged at 1.5K micro-ops (approximately 6KB in size).

Although it's noted above as a new/changed block, the updated instruction decode queue (aka allocation queue) was actually one of the changes made to improve single threaded performance in Ivy Bridge.

The instruction decode queue (where instructions go after they've been decoded) is no longer statically partitioned between the two threads that each core can service.

The big changes in Haswell are at the back end of the pipeline, in the execution engine.

CPU Architecture Improvements: Background Prioritizing ILP
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  • zwillx - Monday, January 21, 2013 - link

    Apple. Or are you joking. I personally hate Apple and have since the original iMac but their engineering is top notch when it comes to getting ideal performance from silicon to user. So.. guessing that's the reference. Reply
  • Silma - Monday, October 08, 2012 - link

    A fine read, technically very comprehensive, but still overly melodramatic.

    While it is true that it is crucial for Intel to step a foot in the byod market some things still hold true:
    - In value and profit the PC processor market is much bigger than the byod processor market and will stay so for years because PCs, especially business PCs won't disappear anytime soon.
    - Nobody can touch Intel in this market, it has been proved for decades. Not AMD at the height of its success, not mighty IBM, not Sun, nobody.
    - Contrary to what you say Intel has a definitive production advantage and there are very few fabs able to compete. Note that Apple is incapable of producing processors, it is dependent on external manufacturers.
    - What Apple does with its processor is interesting business wise for its iPods/Pads/Phones, but Apple doesn't have the research power Intel and others have in the chip space and I can't see how it will innovate better than Intel and other competitors.
    - Intel is aware of its shortcomings, is pushing tremendously in the right direction. A competitor that doesn't rest on its laurels is a mighty threat, ARM beware.
    - If Apple stops using Intel processors, it will of course wipe a few hundred millions of Intel's turnover but won't be anything remotely dangerous for Intel
    - It remains to be seen that Apple users will accept yet another platform change.
    - It remains to be seen that it would make sense business-wise for Apple
    - I am quite sure many phone companies will be open about renewed chip competition and not letting a single platform become too powerful.

    All in all it seems to me Intel is as dangerous as ever, executing very well in its core business and heading towards great things in the phone/pad space.
    Reply
  • johnsmith9875 - Thursday, October 11, 2012 - link

    Why couldn't they at least stick to LGA2011? Reply
  • defiler99 - Tuesday, October 16, 2012 - link

    One of the best articles on Anandtech in some time. This is great original tech industry reporting. Reply
  • Gc - Saturday, January 12, 2013 - link

    Congratulations, an intel cpu engineer wrote around 27 Dec 2012:

    "... Anandtech's latest Haswell preview is also excellent; missing some key puzzle pieces to complete the picture and answer some open questions or correct some details but otherwise great. ..."

    http://www.reddit.com/r/IAmA/comments/15iaet/iama_...
    Reply
  • xaml - Thursday, May 23, 2013 - link

    This was first posted here a few handfuls of pages back as a comment by user "telephone". ^^ Reply
  • yhselp - Friday, March 29, 2013 - link

    A few questions.

    Is there going to be a replacement (37W) for the current IVB 35W quad-core part? Quite a few designs are now dependable on this, lower power quad-core option - Sony S-series and Razer Blade, to name a few.

    When can we expect all mobile CPUs (except maybe for the extreme series) to fall into the 10W-20W range? In three years' time and 10nm?

    The decision to not include GT3 with desktop parts is very disappointing. A 35/45W low-voltage part with GT3 would make for an excellent HTPC build, among other things. Is there a chance Intel change their mind and start shipping GT3 desktop parts at some point?
    Reply

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