CPU Architecture Improvements: Background

Despite all of this platform discussion, we must not forget that Haswell is the fourth tock since Intel instituted its tick-tock cadence. If you're not familiar with the terminology by now a tock is a "new" microprocessor architecture on an existing manufacturing process. In this case we're talking about Intel's 22nm 3D transistors, that first debuted with Ivy Bridge. Although Haswell is clearly SoC focused, the designs we're talking about today all use Intel's 22nm CPU process - not the 22nm SoC process that has yet to debut for Atom. It's important to not give Intel too much credit on the manufacturing front. While it has a full node advantage over the competition in the PC space, it's currently only shipping a 32nm low power SoC process. Intel may still have a more power efficient process at 32nm than its other competitors in the SoC space, but the full node advantage simply doesn't exist there yet.

Although Haswell is labeled as a new micro-architecture, it borrows heavily from those that came before it. Without going into the full details on how CPUs work I feel like we need a bit of a recap to really appreciate the changes Intel made to Haswell.

At a high level the goal of a CPU is to grab instructions from memory and execute those instructions. All of the tricks and improvements we see from one generation to the next just help to accomplish that goal faster.

The assembly line analogy for a pipelined microprocessor is over used but that's because it is quite accurate. Rather than seeing one instruction worked on at a time, modern processors feature an assembly line of steps that breaks up the grab/execute process to allow for higher throughput.

The basic pipeline is as follows: fetch, decode, execute, commit to memory. You first fetch the next instruction from memory (there's a counter and pointer that tells the CPU where to find the next instruction). You then decode that instruction into an internally understood format (this is key to enabling backwards compatibility). Next you execute the instruction (this stage, like most here, is split up into fetching data needed by the instruction among other things). Finally you commit the results of that instruction to memory and start the process over again.

Modern CPU pipelines feature many more stages than what I've outlined here. Conroe featured a 14 stage integer pipeline, Nehalem increased that to 16 stages, while Sandy Bridge saw a shift to a 14 - 19 stage pipeline (depending on hit/miss in the decoded uop cache).

The front end is responsible for fetching and decoding instructions, while the back end deals with executing them. The division between the two halves of the CPU pipeline also separates the part of the pipeline that must execute in order from the part that can execute out of order. Instructions have to be fetched and completed in program order (can't click Print until you click File first), but they can be executed in any order possible so long as the result is correct.

Why would you want to execute instructions out of order? It turns out that many instructions are either dependent on one another (e.g. C=A+B followed by E=C+D) or they need data that's not immediately available and has to be fetched from main memory (a process that can take hundreds of cycles, or an eternity in the eyes of the processor). Being able to reorder instructions before they're executed allows the processor to keep doing work rather than just sitting around waiting.

Sidebar on Performance Modeling

Microprocessor design is one giant balancing act. You model application performance and build the best architecture you can in a given die area for those applications. Tradeoffs are inevitably made as designers are bound by power, area and schedule constraints. You do the best you can this generation and try to get the low hanging fruit next time.

Performance modeling includes current applications of value, future algorithms that you expect to matter when the chip ships as well as insight from key software developers (if Apple and Microsoft tell you that they'll be doing a lot of realistic fur rendering in 4 years, you better make sure your chip is good at what they plan on doing). Obviously you can't predict everything that will happen, so you continue to model and test as new applications and workloads emerge. You feed that data back into the design loop and it continues to influence architectures down the road.

During all of this modeling, even once a design is done, you begin to notice bottlenecks in your design in various workloads. Perhaps you notice that your L1 cache is too small for some newer workloads, or that for a bunch of popular games you're seeing a memory access pattern that your prefetchers don't do a good job of predicting. More fundamentally, maybe you notice that you're decode bound more often than you'd like - or alternatively that you need more integer ALUs or FP hardware. You take this data and feed it back to the team(s) working on future architectures.

The folks working on future architectures then prioritize the wish list and work on including what they can.

Other Power Savings & The Fourth Haswell The Haswell Front End
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  • zwillx - Monday, January 21, 2013 - link

    Apple. Or are you joking. I personally hate Apple and have since the original iMac but their engineering is top notch when it comes to getting ideal performance from silicon to user. So.. guessing that's the reference. Reply
  • Silma - Monday, October 08, 2012 - link

    A fine read, technically very comprehensive, but still overly melodramatic.

    While it is true that it is crucial for Intel to step a foot in the byod market some things still hold true:
    - In value and profit the PC processor market is much bigger than the byod processor market and will stay so for years because PCs, especially business PCs won't disappear anytime soon.
    - Nobody can touch Intel in this market, it has been proved for decades. Not AMD at the height of its success, not mighty IBM, not Sun, nobody.
    - Contrary to what you say Intel has a definitive production advantage and there are very few fabs able to compete. Note that Apple is incapable of producing processors, it is dependent on external manufacturers.
    - What Apple does with its processor is interesting business wise for its iPods/Pads/Phones, but Apple doesn't have the research power Intel and others have in the chip space and I can't see how it will innovate better than Intel and other competitors.
    - Intel is aware of its shortcomings, is pushing tremendously in the right direction. A competitor that doesn't rest on its laurels is a mighty threat, ARM beware.
    - If Apple stops using Intel processors, it will of course wipe a few hundred millions of Intel's turnover but won't be anything remotely dangerous for Intel
    - It remains to be seen that Apple users will accept yet another platform change.
    - It remains to be seen that it would make sense business-wise for Apple
    - I am quite sure many phone companies will be open about renewed chip competition and not letting a single platform become too powerful.

    All in all it seems to me Intel is as dangerous as ever, executing very well in its core business and heading towards great things in the phone/pad space.
    Reply
  • johnsmith9875 - Thursday, October 11, 2012 - link

    Why couldn't they at least stick to LGA2011? Reply
  • defiler99 - Tuesday, October 16, 2012 - link

    One of the best articles on Anandtech in some time. This is great original tech industry reporting. Reply
  • Gc - Saturday, January 12, 2013 - link

    Congratulations, an intel cpu engineer wrote around 27 Dec 2012:

    "... Anandtech's latest Haswell preview is also excellent; missing some key puzzle pieces to complete the picture and answer some open questions or correct some details but otherwise great. ..."

    http://www.reddit.com/r/IAmA/comments/15iaet/iama_...
    Reply
  • xaml - Thursday, May 23, 2013 - link

    This was first posted here a few handfuls of pages back as a comment by user "telephone". ^^ Reply
  • yhselp - Friday, March 29, 2013 - link

    A few questions.

    Is there going to be a replacement (37W) for the current IVB 35W quad-core part? Quite a few designs are now dependable on this, lower power quad-core option - Sony S-series and Razer Blade, to name a few.

    When can we expect all mobile CPUs (except maybe for the extreme series) to fall into the 10W-20W range? In three years' time and 10nm?

    The decision to not include GT3 with desktop parts is very disappointing. A 35/45W low-voltage part with GT3 would make for an excellent HTPC build, among other things. Is there a chance Intel change their mind and start shipping GT3 desktop parts at some point?
    Reply

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