Core Architecture Changes

Ivy Bridge is considered a tick from the CPU perspective but a tock from the GPU perspective. On the CPU core side that means you can expect clock-for-clock performance improvements in the 4 - 6% range. Despite the limited improvement in core-level performance there's a lot of cleanup that went into the design. In order to maintain a strict design schedule it's not uncommon for a number of features not to make it into a design, only to be added later in the subsequent product. Ticks are great for this.

Five years ago Intel introduced Conroe which defined the high level architecture for every generation since. Sandy Bridge was the first significant overhaul since Conroe and even it didn't look very different from the original Core 2. Ivy Bridge continues the trend.

The front end in Ivy Bridge is still 4-wide with support for fusion of both x86 instructions and decoded uOps. The uOp cache introduced in Sandy Bridge remains in Ivy with no major changes.

Some structures within the chip are now better optimized for single threaded execution. Hyper Threading requires a bunch of partitioning of internal structures (e.g. buffers/queues) to allow instructions from multiple threads to use those structures simultaneously. In Sandy Bridge, many of those structures are statically partitioned. If you have a buffer that can hold 20 entries, each thread gets up to 10 entries in the buffer. In the event of a single threaded workload, half of the buffer goes unused. Ivy Bridge reworks a number of these data structures to dynamically allocate resources to threads. Now if there's only a single thread active, these structures will dedicate all resources to servicing that thread. One such example is the DSB queue that serves the uOp cache mentioned above. There's a lookup mechanism for putting uOps into the cache. Those requests are placed into the DSB queue, which used to be split evenly between threads. In Ivy Bridge the DSB queue is allocated dynamically to one or both threads.

In Sandy Bridge Intel did a ground up redesign of its branch predictor. Once again it doesn't make sense to redo it for Ivy Bridge so branch prediction remains the same. In the past prefetchers have stopped at page boundaries since they are physically based. Ivy Bridge lifts this restriction.

The number of execution units hasn't changed in Ivy Bridge, but there are some changes here. The FP/integer divider sees another performance gain this round. Ivy Bridge's divider has twice the throughput of the unit in Sandy Bridge. The advantage here shows up mostly in FP workloads as they tend to be more computationally heavy.

MOV operations can now take place in the register renaming stage instead of making it occupy an execution port. The x86 MOV instruction simply copies the contents of a register into another register. In Ivy Bridge MOVs are executed by simply pointing one register at the location of the destination register. This is enabled by the physical register file first introduced in Sandy Bridge, in addition to a whole lot of clever logic within IVB. Although MOVs still occupy decode bandwidth, the instruction doesn't take up an execution port allowing other instructions to execute in place of it.

ISA Changes

Intel also introduced a number of ISA changes in Ivy Bridge. The ones that stand out the most to me are the inclusion of a very high speed digital random number generator (DRNG) and supervisory mode execution protection (SMEP).

Ivy Bridge's DRNG can generate high quality random numbers (standards compliant) at 2 - 3Gbps. The DRNG is available to both user and OS level code. This will be very important for security and algorithms going forward.

SMEP in Ivy Bridge provides hardware protection against user mode code being executed in more privileged levels.

Motherboard & Chipset Support Cache, Memory Controller & Overclocking Changes
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  • medi01 - Sunday, September 18, 2011 - link

    It's been a while that most users didn't really need faster CPUs or GPUs.
    In a couple of years, why on earth would anyone but gamers need a PC? Emails, browsing, video would be covered by tablets and the likes.
    Reply
  • dealcorn - Friday, November 04, 2011 - link

    My Suzuki Alto has about the horsepower of a team of mules and it's fine, really. However, if for about the same money and fuel economy I could get 600 hp, darn right I need 600 hp. That's about where we are at with CPU power. I believe your issue is more properly stated as "there is a need to re engineer humanity because it is not doing what I want." Reply
  • Billy_Boy - Saturday, September 17, 2011 - link

    "In Sandy Bridge, many of those structures are statically partitioned. If you have a buffer that can hold 20 entries, each thread gets up to 10 entries in the buffer. In the event of a single threaded workload, half of the buffer goes unused."

    If you turn off HT does this go away in Sandy Bridge?
    Reply
  • BioTurboNick - Saturday, September 17, 2011 - link

    They are talking about a hardware implementation, so it wouldn't go away by disabling hyper-threading. Reply
  • Zoomer - Saturday, September 17, 2011 - link

    It depends if the designers thought it would be important enough to implement. Losing 1/2 of the many resources (though probably not execution resources) is huge, and on a non-HT chip it's almost like castrating it. Reply
  • BioTurboNick - Saturday, September 17, 2011 - link

    Right. That's probably why Ivy Bridge is moving to completely single-thread-capable resources. Reply
  • danjw - Saturday, September 17, 2011 - link

    I am wondering if Ivy Bridge will be faster for gaming then the Sandy Bridge-E. I lot of the improvements seem to be with threading, but more games are starting to implement threading. Sandy Bridge-E will have PCI-Express 3.0 and more memory channels, but Ivy Bridge will have faster memory. Reply
  • Hrel - Saturday, September 17, 2011 - link

    Will Intel FINALLY be turning on hyper threading on every CPU? Cause if not that's the final straw that breaks the camels back, I'm going AMD. It took them years to finally get a decent quad core down to 200 bucks, but then if you wanted HT it cost another 100 bucks. Ridiculous. I want to be able to buy a K series quad core with HT for under 200 bucks. Also WHY are there USB 2.0 ports on this AT ALL?

    If AMD has all usb 3.0 ports and the CPU performance is comparable I'm def switching camps.

    Do you guys know if AMD has any plans on releasing SSD caching on their motherboards too? Cause that really is a "killer app" so to speak. Large SSD's are too expensive to make any sense unless you're filthy rich but 64GB with two 2TB HDD's in RAID sounds pretty great.
    Reply
  • philosofool - Saturday, September 17, 2011 - link

    When AMD releases serious competitors at the relevant price points. I hope bulldozer kicks ass, because a solid quad core will be two hundred bucks until there is real competition. Reply
  • medi01 - Sunday, September 18, 2011 - link

    If you count motherboard price in, AMD is already more than competitive. Reply

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