Investigating Sandy Bridge Memory Scaling

Intel's Second Generation Core processors, based on the Sandy Bridge architecture, include a number of improvements over the previous generation's Nehalem architecture. We’ll be testing one specific area today: the improved memory controller. Current Sandy Bridge based processors officially support up to DDR3-1333 memory. Unfortunately, due to changes in the architecture, using faster rated memory (or overclocking memory) on Sandy Bridge via raising the base clock is extremely limited. Luckily, there are additional memory multipliers that support DDR3-1600, DDR3-1866, and DDR3-2133 memory. Some motherboards include support for even higher memory multipliers, but we’ll confine our investigations to DDR3-2133 and below.

Since Sandy Bridge is rated for up to DDR3-1333 memory, we will start there and work our way up to DDR3-2133 memory. We'll also be testing a variety of common CAS latency options for these memory speeds. Our purpose is to show how higher bandwidth memory affects performance on Sandy Bridge, and how latency changes—or doesn’t change—the picture. More specifically, we’ll be looking at the impact of memory speed on application and gaming performance, with some synthetic memory tests thrown into the mix. We’ll also test some overclocked configurations. So how much difference will lowering the CAS latency make, and does memory performance scale with processor clock speed?

Back when I originally envisioned this comparison, the price gap between DDR3-1333 and DDR3-2133 memory was much wider. A quick scan of Newegg reveals that a mere $34 separates those two 4GB kits. Below is a breakdown of the lowest prices (as of 7/16/2011) for various memory configurations.

4GB 2x2GB Kits
DDR3-1333 CL9 $31
DDR3-1333 CL8 $40
DDR3-1600 CL9 $40
DDR3-1600 CL8 $41
DDR3-1333 CL7 $45
DDR3-1600 CL7 $50
DDR3-1866 CL9 $60
DDR3-2133 CL9 $65


8GB 2x4GB Kits
DDR3-1333 CL9 $58
DDR3-1600 CL9 $66
DDR3-1333 CL7 $75
DDR3-1600 CL8 $80
DDR3-1866 CL9 $85
DDR3-1600 CL7 $115
DDR3-2133 CL9 $150

You can see from the above chart that balancing memory clocks with latency results in some interesting choices, particularly on the 8GB kits where price differences are a bit larger. Is it best to go with a slower clock speed and better timings, or vice versa, or is the optimal path somewhere in between? That’s the aim of this article.

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  • mga318 - Monday, July 25, 2011 - link

    You mentioned Llano at the end, but in the Llano reviews & tests, memory bandwidth was tested primarily with little reference to latency. I'd be curious as to which is more important with a higher performance IGP like Llano's. Would CAS 7 (or 6) be preferrable over 1866 or 2166 speeds wtih CAS 8 or 9? Reply
  • DarkUltra - Monday, July 25, 2011 - link

    How about testing Valves particle benchmark or a source based game at low reslution with a non-geometry limited 3d card (fermi) and overclocked cpu? Valve did an incredible job with their game engine. They used a combination of fine-grained and coarse threading to max out all the cpu cores. Very few games can do that today, but may in the future. Reply
  • DarkUltra - Monday, July 25, 2011 - link

    Why test with 4GB? RAM is cheap, most people who buy the premium 2600K should pair it with two 4GB modules. I imagine Windows would require 4GB ram and games the same in the future. Just look at all the .net developers out there, .net usually results in incredible memory bloated programs. Reply
  • dingetje - Monday, July 25, 2011 - link

    hehe yeah
    .net sucks
    Reply
  • Atom1 - Monday, July 25, 2011 - link

    Most algorithms on CPU platform are optimized to have their data 99% of time inside the CPU cache. If you look at the SisSoft Sandra where there is a chart of bandwidth as a function of block size copied you can see that CPU cache is 10-50x faster than global memory depending on the level. Linpack here is no exception. The primary reason for success of linpack is its ability to have data in CPU cache nearly all of the time. Therefore, if you do find an algorithm which can benefit considerably from global memory bandwidth, you can be sure it is a poor job on the programmers side. I think it is a kind of a challenge to see which operations and applications do take a hit when the main memory is 2x faster or 2x slower. I would be interested to see where is the breaking point, when even well written software starts to take a hit. Reply
  • DanNeely - Monday, July 25, 2011 - link

    That's only true for benchmarks and highly computationally intensive apps (and even there many problem classes can't be packed into the cache or written to stream data into it). In the real world where 99% of software's performance is bound by network IO, HD IO, or user input trying to tune data to maximize the CPU cache is wasted engineering effort. This is why most line of business is written using java or .net, not C++; the finer grained memory control of the latter doesn't benefit anything while the higher level nature of the former allows for significantly faster development. Reply
  • Rick83 - Monday, July 25, 2011 - link

    I think image editing (simple computation on large datasets) and engineering software (numerical simulations) are two types of application that benefit more than average from memory bandwidth, and in the second case, latency.
    But, yeah, with CPU caches reaching the tens of Megabytes, Memory bandwidth and latency is getting less important for many problems.
    Reply
  • MrSpadge - Wednesday, July 27, 2011 - link

    True.. large matrix operations love bandwidth and low latency never hurts. I've seen ~13% speedup on part of my Matlab code going from DDR3-1333 CL9 to DDR3-1600 CL9 on an i7 870!

    MrS
    Reply
  • Patrick Wolf - Monday, July 25, 2011 - link

    You don't test CPU gaming benchmarks at normal settings cause you may become GPU limited so why do it here?
    http://www.xbitlabs.com/articles/memory/display/sa...
    Reply
  • dsheffie - Monday, July 25, 2011 - link

    ....uh...Linpack is just LU which in turn is just DGEMM. DGEMM has incredible operand reuse (O(sqrt(cache size)). Reply

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