Boxee Box: The Inside Story, Swapping Tegra 2 for Intel CE4100

The Intel CE4100 (codenamed Sodaville) was introduced on September 24, 2009 at the Intel Developer Forum. Based on the Atom CPU, it is a full blown SoC. A basic block diagram of the CE4100 is shown below.

The x86 core in the SoC is based on the Atom CPU. We suspect that the CE4100 is a slightly modified single die implementation of the Lincroft and Langwell SOCs used in Moorestown, albeit in the 45nm process. While the Moorestown platform had a 32 bit DDR interface, the CE4100 increases this to 64. Other than that, the core components for the OpenGL and video decode support seem to be the same.

The Atom core with 512K of L2 cache is the host processor in the SoC. Though the internal L1 cache details are not public, it is likely to be the same as that of the Lincroft SoC which had 24K of data cache and 32K of instruction cache. Owing to a single die implementation, as well as the process geometry, the TDP of the SoC must be a bit high compared to Lincroft or Langwell taken alone. The higher DRAM bus width also contributes to an increase in the TDP.

The memory controller can support two separate channels of 32-bit DDR2-800/DDR3-1333. This is in contrast to the single channel 32 bit DRAM support in the Tegra 250 which was the earlier SoC under consideration. A NAND flash controller helps the system boot from attached Flash storage. The ability to boot from NAND flash has the potential to reduce the board costs.

Next, we shift our attention to the most interesting gray box in the diagram. This block consists of the video decoder, display processor and the graphics processor. While the block diagram removes any doubt that the graphics processor used is the same as the one used in the iPhone 4 (Imagination Technologies PowerVR SGX535), the origins of the other two components are not entirely clear. We have been led to believe that Imagination Technologies is behind these components as well. The decoder would be a member of the PowerVR VXD series, and it is indicated that two simultaneous HD streams can be decoded. There is also hardware acceleration for decoding JPEG pictures, so one may possibly look forward to snappy photo slideshows in products using this SoC. The scaling, noise reduction and deinterlacing features of the display processor need proper programming in order to be able to deliver good results, and the quality of the Intel drivers would ultimately decide the HQV scores for media streamers based on this SoC. The display controller also needs proper configuration in case a product based on this SoC is supposed to end up supporting native frame rates. It is also responsible for OSD blending, subtitles and miscellaneous video functions.

From the perspective of the Boxee Box, the Audio/Video inputs go unused. However, using this SoC in a DVR / PVR system would make the usage of these inputs necessary. For media streamers, HDMI 1.3a is the key feature. Considering that this SoC was launched almost one year back, the absence of HDMI 1.4 is excusable. For general I/O, we have GbE support, but the Boxee Box only enables 100 Mbps Ethernet. The 2 SATA ports also go unused, but both the USB 2.0 host ports are taken advantage of. Some of the other I/O ports are configured for supporting SDIO. Without a look at the board, and knowledge of the pin configuration, it is not evident which I/Os are configured for supporting the SD card.

The CE4100 also sports a dual audio DSP from Tensilica, the Tensilica HiFi2. It is capable of downmixing / decoding two lossless HD audio streams (as per Blu-Ray bitrate specifications) simultaneously. The Transport Processor would be useful for a STB product. We have been given to understand that the security processor is not disabled in the Boxee Box. This should enable the Boxee Box to access premium online content and also get a license from the Blu-Ray consortium.