Manufacturing, Die Size and Clock Speed

Intel's superiority in manufacturing is responsible for the majority of their technological advances in microprocessors over the past decade, and it's often argued that there isn't a company around that could come close to matching Intel's manufacturing abilities - with the exception of IBM.

The Cell prototype boasts some pretty major manufacturing specs:

- 90nm SOI manufacturing process
- 221 mm2 die area
- 234M transistors
- > 4GHz observed clock speed

When it was first announced, the chip sounded massive, but its specifications compare extremely well to Intel's upcoming Pentium D processor; let's take a look at its vitals:

Intel Pentium D Processor

- 90nm strained silicon manufacturing process
- 206 mm2 die area
- 230M transistors
- 2.8GHz - 3.2GHz clock speed

With a slightly larger chip and a few million transistors more, Cell is supposed to be able to run at a minimum of 25% higher clock frequency than Intel's forthcoming Pentium D.   We'll let that sit in for a moment...

Dynamic Logic

At first glance, a 90nm SOI Cell running at between 3 - 5GHz looks extremely impressive.   After all, the fastest 90nm CPU IBM currently produces runs at 2.5GHz, not to mention that even Intel, the king of clock speed, can't mass produce anything faster than 3.8GHz on their 90nm process.   But let's dig a little deeper.

The Pentium 4 has two ALUs that run at twice its internal clock speed - so in the case of a Pentium 4 660, that means that two of the more frequently used execution units operate at 7.2GHz - on a 90nm process.   So, it's possible to get circuits to run at higher clock speeds, even in the 3 - 5GHz range, on current 90nm processes - it just takes a little bit of creative logic design.

It's been confirmed that Cell is using some sort of dynamic logic as opposed to static CMOS in order to control transistor counts and improve operating frequencies.   Intel uses a number of specialized logic techniques in their double-pumped ALUs to reach their 7GHz+ operating frequencies, and Intel has discussed techniques that are similar to the dynamic logic used in Cell.


The diagram on the right of a "sleep transistor" should look very familiar by the end of this article

To understand how dynamic works, you have to understand how the transistors are implemented on a chip.

Transistors and You

Just about any AnandTech reader who has followed our CPU articles has heard us count transistors before, but understanding how transistors work is quite critical to understanding how IBM can talk about 3 - 5GHz clock speeds for Cell.

We'll spare you the details about how transistors are made and the physics behind them in an attempt to keep this section as brief, but as informative, as possible.   It's quite common to refer to a transistor as a "switch" much like a light switch, so how does a transistor function like a switch?   Below, we have a representation of a p-type transistor:

There are three points labeled on the transistor: the drain (D), gate (G), and source (S).   In a microprocessor, you generally have the source connected to Vcc (think of Vcc as a line carrying the CPU's core voltage), and the drain connected to ground - often times indirectly (e.g. 10 transistors will be connected in series, with the top-most source connecting to Vcc and the bottom-most drain connecting to ground).

The input to the gate of the p-type transistor is what makes it function as a switch.   If you apply the right voltage to the gate, thus making it a logical "1" or high, current doesn't flow in the transistor.   If you don't apply any voltage to the gate, current can flow.   Just like a light switch, flip it one way and the light turns on; flip it another and you're in the dark.

There's another type of transistor that we'll be talking about here: the n-type transistor:

The three points on the transistor are the same, but the drain and source switch places.   The functionality of the n-type transistor is different as well.  Here, if you apply the appropriate voltage to the gate, a current will flow; if you apply no voltage, no current will flow through the transistor.

CMOS circuits work by using pairs of n- and p-type transistors (that's where the Complementary element of CMOS comes from).   CMOS circuits are by far the most predominant in modern day microprocessors, but as you will soon see, that doesn't mean that they are without flaws.

Cell's Approach - In Order with no Cache Understanding Gates
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  • Poser - Thursday, March 17, 2005 - link

    There were moments while reading this article that I expected there to be a "Test Yourself" quiz at the end of the chapter ... er, article. Which isn't to say that articles like this are too textbookish, it's to say that they're wonderfully educational. And very, very cool for being so.

    I'm half joking when I say this (but only half) -- a real "test" at the end of the article would be fun. I could see if I really understood what I read, and even get to compare my score to the rest of the, uhm, class.
  • drinkmorejava - Thursday, March 17, 2005 - link

    very nice, how long did it take to write that thing?
  • Eug - Thursday, March 17, 2005 - link

    #42,

    That's an interesting page, cuz everyone on OS X already knows that Word is slow on the Mac. It brings us back to the original statement that some ported software may be problematic performance-wise.

    And the generic comment on the Mac side about Premiere is, well... use Final Cut Pro. :) Here is a test that seems a bit more useful, since it tests Cinema4D and After Effects, two apps that people use on the Mac and both of which are reasonably well optimized:

    http://digitalvideoediting.com/articles/viewarticl...

    That's a good point about the memory scaling though. The IMC with AMD's chips is a definite advantage. I'm sure the G5 970MP dual-core won't get an IMC either.

    Anyways, as far as this article is concerned, the G5 is kinda irrelevant. The interesting part for Apple in Cell is the PPE unit. It's also interesting that Anand says the original SPE was supposed to be VMX/Altivec. But the current SPE is not Altivec so it's less applicable for Apple, at least in the near term.

    It would be interesting to know how fast a dual-core 3 GHz PPE would be in general laptop-type code, and how much power it would put out.
  • MDme - Thursday, March 17, 2005 - link

    #39, 40, 41

    http://www.pcworld.com/news/article/0,aid,112749,p...

    remember that the athlon 64 chips scale better at higher clock speeds due to the mem controller scaling as well.

  • Eug - Thursday, March 17, 2005 - link

    Well, one example is Cinebench 2003:

    The dual G5 2.0 GHz is about the same speed as a dual 0pteron 246 2.0 GHz, with a score at around 500ish.

    http://www.aceshardware.com/read.jsp?id=60000284

    BTW, a dual G5 2.5 GHz scores 633.
  • suryad - Thursday, March 17, 2005 - link

    Hmm that is interesting what you say Eug. I see your point do you have any links on straight comparos between an FX and a top of the line Mac? Or from personal experience folding and such...
  • Eug - Thursday, March 17, 2005 - link

    #38. It's a mistake to say an AMD FX 55 smokes a dual G5 2.5. For instance, if you like scientific dual-threaded stuff, the G5 does very well. However, the AMD FX 55 IS faster than a single G5 2.5. It's got a slight edge clock-for-clock, and it's clocked slightly higher too.

    The real problem is when you have stuff built for x86 ported over to PPC. It just isn't great on the Mac side performance-wise in that situation. And Macs aren't tweaked for gaming either. The AMD is going to smoke the Mac in Doom 3 of course.

    I think with the performance advantage of the Opteron, I'd put a single G5 2.5 in the range of performance of a single Opteron 2.2-2.4 GHz, depending on the app. The real interesting part though will be the coming quarter, when the new G5s are released. They should get a significant clock speed bump (20%?) and information on dual-core G5s are already out there (like with AMD and their dual-core Athlons). They also get a cache boost. Right now they only have 512 KB, but are expected to get 1 MB L2.
  • suryad - Thursday, March 17, 2005 - link

    Well scrotemaninov I am not disputing that the POWER architecture by IBM is brilliantly done. IBM is definitely one of those companies churning out brilliant and elegant technology always in the background.

    But my problem with the POWER technology is from what I understand very limitedly, is that the POWER processors in the Mac machines are a derivative of that architecture right? Why the heck are they so damn slow then?

    I mean you can buy an AMD FX 55 based on the crappy legacy x86 arch and it smokes the dual 2.5 GHz Macs easily!! Is it cause of the OS? Because so far from what I have seen, if the Macs are any indication of the performance capabilities of the POWER architecture, the Cell will not be a big hit.

    I did read though at www.aceshardware.com benchmark reviews of the POWER5 architecture with some insane number of cores if I recall correctly and the benchmarks were of the charts. They are definitely not what the Macs have installed in them...
  • scrotemaninov - Thursday, March 17, 2005 - link

    #35: different approaches to solving the same problem.

    Intel came up with x86 a long time ago and it's complete rubbish but they maintain it for backwards compatibility (here's an argument for Open Source Software if ever there was one...). They have huge amounts of logic to effectively translate x86 into RISC instructions - look at the L1I Trace Cache in the P4 for example.

    IBM aren't bound by the same constraints - their PowerPC ISA is really quite nice and so there's no where near the same amount of pain suffered trying to deal with the same problem. It does seem however, that IBM are almost at the point that Intel want to be in 10 years time...
  • Verdant - Thursday, March 17, 2005 - link

    here is a question...

    it mentions (or alludes) in the article that having no cache means that knowing exactly when an instruction would be executed is possible, is the memory interface therefore a strict "real time system" ?

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