AMD Begins Tape-Out of first Dual Core Opteronby Anand Lal Shimpi on June 14, 2004 4:15 PM EST
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Continuing to ride the train of success that AMD has had in 2004, AMD is announcing today the completion of design work on their first dual-core Opteron processor and the beginning of the tape-out process for that core. While the first dual core CPUs won't be available until the middle of next year at the earliest, AMD sees the beginning of the first dual core tapeout as a pretty monumental step in their microprocessor evolution.
AMD is not providing much information about the new dual core CPUs other than a low-resolution die shot and a roadmap; luckily we can derive a decent amount of information from the die shot, so let's get to it.
First, here's a shot of a current generation 130nm Opteron die:
You can see that the majority of the functional units are on the left of the die and the L2 cache and the 128-bit memory interface are both on the right of the die. Now let's take a look at the finalized design for the first 90nm dual core Opteron die:
As we mentioned earlier, the image is relatively low-res so you can't see much detail in it but you should be able to see two distinct cores. Although AMD isn't commenting on any of the details of the implementation, it appears as if the first dual core Opterons are basically two Opterons connected together on a single die - meaning each core has its own L2 cache. Here's a good idea of what you're probably seeing above:
The DDR memory interface appears to wrap around both L2 caches, meaning that it looks like both cores have their own 128-bit memory interface; whether or not both memory controllers will be enabled is another thing, but if this is true we have a number of implications to talk about.
If dual core Opterons do indeed have two memory controllers, the pincount of dual core Opterons will go up significantly - it will also make them incompatible with current sockets. AMD is all about maintaining socket compatibility so it is quite possible that they could only leave half of the memory controllers enabled, in order to offer Socket-940 dual core Opterons. AMD isn't being very specific in terms of implementation details, but these are just some of the options.
AMD did mention that they will eventually start referring to Opteron server configurations according to the number of sockets, not CPUs, the platform is capable of supporting. For example, a 1 socket Opteron server could either be a 1-way or a 2-way configuration, depending on whether a single or dual core Opteron is used.