Genoa

JEDEC still has not published the DDR5 specification officially, yet it looks like DRAM makers and SoC designers are preparing for the DDR5 launch at full steam. Cadence, which was vocal about the new technology back in 2018, and has since released provisional DDR5 IP (the DDR5 controller and PHY) commercially, this week presented some additional information about the upcoming DDR5 market release as well as the technology's progress. DDR5 Platforms Getting Ready On the SoC side of matters, we already know that AMD’s EPYC ‘Genoa’ as well as Intel’s Xeon Scalable ‘Sapphire Rapids’ will support DDR5 DRAM when they launch in the 2021 ~ 2022 timeframe. What is noteworthy, is that Cadence’s provisional DDR5 IP has ‘over a dozen design-ins’, so there are over 12...

Updated AMD Ryzen and EPYC CPU Roadmaps March 2020: Milan, Genoa, and Vermeer

Everyone is interested in roadmaps – they give us a sense of an idea of what is coming in the future, and for the investors, it gives a level...

60 by Dr. Ian Cutress on 3/5/2020

AMD Moves From Infinity Fabric to Infinity Architecture: Connecting Everything to Everything

Another element to AMD’s Financial Analyst Day 2020 was the disclosure of how the company intends to evolve its interconnect strategy with its Infinity Fabric (IF). The plan over...

18 by Dr. Ian Cutress on 3/5/2020

An Interview with AMD’s Forrest Norrod: Naples, Rome, Milan, & Genoa

There’s no getting away from the fact that AMD’s big revenue potential exists in the server space. While the glitz and the glamor is all about the Ryzen, the...

49 by Dr. Ian Cutress on 6/24/2019

AMD Confirms Zen 4 EPYC Codename, and Elaborates on Frontier Supercomputer CPU

After the Computex Keynote today on stage, where AMD revealed its new Ryzen family of processors coming on 7/7, we had a chance to speak with AMD’s SVP and...

16 by Ian Cutress on 5/27/2019

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