The Gen-Z Consortium this week released Physical Layer Specification 1.1 for Gen-Z interconnects. The new standard adds enhanced support for PCIe Gen 5 as well as Gen-Z 50G Fabric and Local PHY. The publication of the new PHY revision enables chip developers to implement support for the technologies in upcoming devices featuring Gen-Z interconnects. Designed to offer high bandwidth and low latency for connections between processors, co-processors/accelerators, and memory/fast storage, Gen-Z 1.0 uses a PCIe physical layer and a modified IEEE 802.3 Ethernet electrical layer standards to provide per-lane speeds of up to the 56 GigaTransfers/second. The Gen-Z 1.0 physical layer specification only defined usage of PCIe Gen 1-4 protocols as well as a 25 GT/s PHY. Thus, to take advantage of all the capabilities...
One of the key competing interconnects of the future is Gen-Z, and Hewlett Packard Enterprise have a Gen-Z chipset to show at Hot Chips today.2 by Dr. Ian Cutress on 8/20/2019
SMART Modular this month demonstrated one of the industry’s first prototypes of a EDSFF 3-inch DDR4 Gen-Z memory module. The ZMM supports advanced functionality enabled by the new interface...16 by Anton Shilov on 8/15/2019
Hot Chips 31 (2019) Programme Announced: Zen, Navi, POWER, Lakefield, Gen-Z, Turing, Lisa Su Keynote
There are two trade shows every year that I love. Computex in June is great, because the scale of the industry it covers, and Taipei is a wonderful location...17 by Ian Cutress on 5/16/2019
The first major release of the Gen-Z systems interconnect specification is now available. The Gen-Z Consortium was publicly announced in late 2016 and has been developing the technology as...23 by Billy Tallis on 2/13/2018
Anyone tasked with handling the way data is moved around a processor deserves praise. It takes time, dedication and skill to design something that not only works appropriately and...15 by Ian Cutress on 10/12/2016