CXL

AMD's CTO, Mark Papermaster, has published a blog post this week said that AMD has joined the Compute Express Link (CXL) Consortium. The industry group is led by a set of nine industry giants such as Intel, Alibaba, Google, and Microsoft. The CXL 1.0 technology uses the PCIe 5.0 physical infrastructure to enable a coherent low-latency interconnect protocol that allows to share CPU and non-CPU resources efficiently and without using complex memory management. The announcement indicates that AMD now supports all of the current and upcoming high-speed interconnect protocols, including CCIX, Gen-Z, and OpenCAPI.

Compute Express Link (CXL): From Nine Members to Thirty Three

Last month the CXL Specification 1.0 was released as a future cache coherent interconnect that uses the PCIe 5.0 physical infrastructure but aimed to provide a breakthrough in utility...

18 by Ian Cutress on 4/15/2019

Intel Agilex: 10nm FPGAs with PCIe 5.0, DDR5, and CXL

Ever since Intel purchased Altera for an enormous amount of money a few years ago (ed: $16.7B), the FPGA portfolio that has been coming out has largely been a...

12 by Ian Cutress on 4/2/2019

CXL Specification 1.0 Released: New Industry High-Speed Interconnect From Intel

With the battleground moving from single core performance to multi-core acceleration, a new war is being fought with how data is moved around between different compute resources. The Interconnect...

46 by Ian Cutress on 3/11/2019

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