Intel Introduces 533MHz FSB CPUs - Pentium 4 2.53GHzby Anand Lal Shimpi on May 6, 2002 12:00 PM EST
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A new FSB requires a new chipset?
The Pentium 4 debuted with the i850 chipset which only carried official support for a 100MHz clocked quad-pumped FSB. The "quad-pumped" nature of the bus indicated that data was transferred four times per clock, twice on the rising edge and twice on the falling edge. As you can expect, with a quad-pumped FSB there are very strict electrical guidelines that must be followed in order to ensure that the correct data gets transferred at the right time during every clock cycle. Although it's very easy to say "400MHz FSB," the amount of effort put into validation to make sure that the chipsets, motherboards and CPUs work with a quad-pumped bus is incredible. We put together this little diagram to help you understand why:
The three images you see above are pictures of a 100MHz rectangular pulse train similar to what the FSB and other clocks in your system operate off of. Since all of the signals run at 100MHz, the time between two rising edges is 10ns. What does a rising edge actually signify? It represents the change from low to high voltage; low is usually defined as a voltage close to 0 while high can vary depending on the platform which in this case is around 1.6V.
The first signal is only triggered once per clock cycle (10ns) meaning that the chipset only has to detect a voltage close to 1.6V in order to initiate a data transfer.
The second signal is triggered twice per clock cycle, once on the rising edge and once on the falling edge. This becomes a little more complicated as the logic must now transfer data twice every 10ns but it has to detect when the voltage is increasing towards 1.6V and then once again when it's decreasing towards 0V. Double-pumped or DDR signaling requires a bit more effort to test and ensure proper operation under all conditions.
The final case is by far the most complex to implement of the three because now the chipset must detect four different voltages. The first two occur somewhere between 0 and 1.6V on the rising edge of the clock, and the other two occur in the same range but on the falling edge. If we assume that 0 - 0.7V defines one part of the rising edge of the clock and 0.8 - 1.6V defines the other part, you can see how the signal must be fairly consistent in order to properly enable four data transfers per clock cycle. It is already difficult enough to distinguish high from low when the spread is only 1.6V wide, but trying to distinguish two different values on each edge of the clock is even worse.
Now let's say we increased the frequency of the FSB from 100MHz to 133MHz; that seems like such a small increase but now all of the circuitry and logic has 25% less time (7.5ns vs. 10ns) to transfer data four times and prepare for the next set of data transfers. The actual modifications that needed to be made to the i850 chipset in order to allow for 133MHz FSB clock speeds were minimal; however the biggest limitation by far was validating the chipsets (ensuring that they would work flawlessly at 133MHz).
This is one situation in which Intel's strict validation policies put users in a bit of a bind. Currently, the vast majority of i850 chipsets work just fine at a 133MHz FSB frequency but definitely not all. From this point on however, all Pentium 4 processors will be using the 133MHz FSB. What are end users to do? If you have a recent i850 board then chances are it already works fine at the 133MHz FSB, but in order to meet Intel's validation requirements a new chipset with official support for the FSB had to be produced - the i850E.
Intel's 850E Memory Controller Hub
The i850E is no different from the i850 from a feature standpoint other than its official support for the 133MHz quad-pumped FSB. Electrically, it's nearly identical to the i850 with minor modifications to ensure that it will fully pass Intel's validation specifications at the increased FSB frequency.