Samsung SSD 850 EVO (120GB, 250GB, 500GB & 1TB) Reviewby Kristian Vättö on December 8, 2014 10:00 AM EST
Three Bits and Three Dimensions: What's the Deal?
I've covered 3D NAND and TLC NAND in detail in the past and in this article I'll just explain what 3D technology means to TLC NAND and vice versa, so head over to the links above if you are in the search for a deeper analysis of the two technologies.
Truth to be told, 3D technology is ideal for TLC. The fundamental problem of TLC NAND has always been the limited endurance and performance, which is caused by the additional voltage states that are needed to store three bits (i.e. eight possible bit outputs) in one cell. With eight voltage states compared to four in MLC, TLC NAND is less resistant to wear out because it takes a smaller change in the cell charge to corrupt the cell value. Due to the way NAND works, the cells (or the insulators in the cell to be exact) wear out over time, which induces electron leakage that alters the cell charge and hence the voltage state. This gets worse with die shrinks because the number of electrons decreases, making the NAND even less tolerant to wear out.
The key aspect of 3D V-NAND is the process node. By going back to 40nm lithography, the number of electrons increase exponentially, which makes TLC a much more viable technology than it was with modern planar NAND. Obviously, V-NAND doesn't change the basics of TLC NAND because it still takes eight voltage states to differentiate all the possible 3-bit outputs, but thanks to the increased number of electrons there is more breathing room between the states and thus the cells are more error tolerant.
Samsung claims 10x reduction in voltage state overlaps, which is a massive change for the better. You can see how crammed the planar TLC voltage states are, so it's no wonder that the endurance is low because the states are practically overlapping at each point in the voltage distribution and hence even tiny changes in the cell voltage can alter the cell's voltage state.
The larger cell structure also enables higher performance because it takes less iterations to program a cell. With planar TLC NAND it took multiple very high voltage pulses as well as numerous verification process to reach the right charge, but with looser voltage distribution the programming process has less steps and thus takes less time.
And given the lower read/program latencies and less need for error correction, the power consumption is also considerably lower.
In addition to better latency and power consumption characteristics, Samsung claims doubled the density over its 19nm planar TLC NAND, but without knowing the die size of 128Gbit 32-layer TLC V-NAND, it's hard to say how accurate this is. There have been some whispering that the 128Gbit die would actually be identical to the 86Gbit MLC die because 86Gbit multiplied by 1.5 equals 129Gbit and at the silicon level MLC and TLC aren't any different, but for now that's just speculation.
What I do know is that Samsung started the mass production of TLC V-NAND later, which suggests that the two aren't completely uniform. Moreover, from what I know TLC NAND requires some changes to the peripheral circuitry in order to read three bits from one cell, so while the NAND memory arrays could be alike the die size is still likely at least slightly different. Anyway, we'll find out when Chipworks (or some other silicon analysis company) takes a closer look at the NAND die itself.