Socket-A Chipset Roundup - August 2001by Anand Lal Shimpi on August 21, 2001 3:42 AM EST
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Memory Bandwidth & Latency - Cachemem
The cachemem tests show similar results, although erring much more on the theoretical maximum end of the spectrum rather than somewhat realistic maximums. Here the difference between the SiS 735 and AMD 760 grows to 14%.
Writing to main memory takes a lot more work than simply reading from it, hence you get much lower peak bandwidths. The standings change a bit, with the AMD 760 coming out on top and the SiS 735 equipped with PC133 SDRAM distancing itself from the KT266.
And now to put sense to it all. Where memory bandwidth isn’t necessary for high performance, low memory latency is the key to success. The last time we visited latencies of Socket-A memory controllers we concluded that it would be very tough for VIA to beat AMD in designing such an efficient DDR memory controller. We cited AMD’s experience with Super Bypass functions and other latency reducing techniques in their chipsets as an advantage that VIA would not have. When looking only at AMD and VIA, we were right; even shipping KT266 boards are not able to offer lower latency memory accesses than the AMD 760.
However, when you throw the SiS 735 into the fray things change considerably. The 735 offers 17% lower latency memory accesses than even the AMD 760. Not to mention the 30% advantage it has over the KT266.
You’ll also note that the KT266 shows higher latencies than the PC133 equipped KT133A. This isn’t out of the ordinary as DDR SDRAM does have slightly higher latencies and regular SDRAM. This is why there is very little performance difference, sometimes in favor of the KT133A, in applications that aren’t memory bandwidth intensive.