5) With the growing bandwidth demands being placed on the chipsets in today's PCs, what are your plans for a higher bandwidth interconnect between the North/South Bridges. V-Link currently provides 266MB/s of bandwidth which is definitely enough for the majority of situations that it is used in, but looking towards the future will V-Link be abandoned in favor of HyperTransport or do you plan on updating the V-Link specification to provide for the added bandwidth requirements?
We're not planning to abandon V-Link - quite the contrary in fact. V-Link still has a lot of headroom in its bandwidth. Right now, it is implemented with an 8-bit bus at 66MHz, quad data pump per CLK cycle. But it could be implemented with 16-bit or 32-bit data bus width, and the speed could go 133MHz or even higher. HyperTransport looks to be a very interesting solution for a variety of different applications and we are carefully evaluating it at the moment.
6) A major problem in today's chipsets is the inherent latency associated with having to go through the North Bridge every time the CPU wants to perform a memory access. Micron has been an advocate of the use of some of the North Bridge's packaging space for integrating an on-die "L3 cache" to improve performance. What are VIA's thoughts on such an option and is it something that you may be exploring in the future?
L3 cache is just a part of the solution to reduce the CPU-memory access latency issue. The most advanced CPU bus protocols already consider the core/bus speed difference, so a split bus, out-order reply cycle, and deep outstanding bus buffer are common practices to hide the bus latency while pipelining/overlapping the CPU request cycles. So we believe that DRAM latency is not as serious an issue as most people think and that increasing memory bandwidth may have a bigger impact on overall system performance.
Having said that, however, we have to look at all possible avenues for boosting overall system performance, and believe that L3 cache is clearly a viable solution for speeding up CPU-DRAM access. We have built up strong expertise and technology for developing a cost effective L3 cache solution, but are studying the L3 cache architecture, data coherency protocol, snoop latency, and performance impact before we add an L3 cache into our chipsets.
7) What are VIA's thoughts on the future of DDR memory in the performance PC market segment? Application bandwidth requirements are increasing and there will be a time when even the 2.1GB/s of bandwidth offered by DDR won't be enough. Where does VIA see the memory market going after DDR? Dual Channel DDR, DDR-II, Rambus or Yellowstone (Rambus' next generation technology)?
The next step will be DDR 333 followed by DDR-II; the specs for this are currently being discussed by JEDEC. We've been saying for years that we don't see Rambus ever gaining serious traction in the mainstream PC market, and nothing has happened over the past few months to change that view. DDR, on the other hand, is now gaining strong momentum as prices have come down and more and more DDR motherboards have become available. I hear that Yellowstone Park is a nice place to take a vacation.
8) Intel's i860 chipset features a prefetch cache on the Memory Controller Hub (MCH), is this something that the P4X266 may have as well?
Actually, we've had a similar design in our chipsets since our x486 processor products! We call it a Memory Prefetch Buffer. We have prefetch buffers implemented that are not only limited to CPU-to-DRAM access, but also cover the PCI-to-DRAM assess cycle.
9) One of the biggest complaints that users had of VIA during the early days of the Apollo Pro 133/133A was that with VIA chipsets you had to install chipset drivers while with Intel chipsets you didn't have to. Although this was a common misconception (Intel chipsets required drivers too, some were built into Windows' driver libraries) it did raise an interesting point, how closely are VIA and Microsoft working to make sure that future releases of Microsoft OSes such as Windows XP will have solid support for VIA chipsets?
We've worked very closely with Microsoft to make sure that all our drivers are included in Windows XP. It's a great operating system - and will deliver really solid support for our chipsets.
10) Having recently entered the server market in competition to Transmeta's low powered server platforms (TM5400, TM5600 and TM5800), how do you see the VIA C3 penetrating into that market?
We're very pleased with the response we have received from our server customers so far. Many of them have said that the power consumption of the VIA C3 is lower than that of the Crusoe, and its Socket 370 compatibility gives them a lot more flexibility in terms of design and configuration. Another key advantage we have in this space is that we can provide a complete platform; we are seeing a number of designs where customers are combining the VIA C3 with our VIA Apollo Pro266 chipset. With DDR running at a lower voltage than PC133 SDRAM, this provides a lower power yet higher performance combination.
If there's anything else you would like to add feel free to do so. I appreciate your time and cooperation and good luck in the future.
I'd just like to close this Q&A session by thanking you very much for giving me this opportunity to communicate with your readers. If they have any questions, they should feel free to send me an email at RichardBrown@via.com.tw. I will do my best to answer them.