Tile Based Rendering: PowerVR's Solution
The PowerVR approach, as mentioned above, is known as tile based rendering and differs significantly from immediate mode rendering when it comes to constructing a 3D scene. The tile based rendering approach attempts to eliminate any redundant processing in the 3D pipeline, thereby significantly reducing the memory bandwidth limitations that currently plague the video card industry and their immediate mode rendering approach.
Rather than process one polygon at a time without knowledge of other polygons in the scene, a tile based renderer first groups polygons together in groups called display lists. These display lists allow a scene to be broken into smaller blocks, known as tiles, which are then rendered independently.
The first advantage to rendering smaller portions of a scene at once is that it allows operations to be performed on-chip without having to access external memory. This allows all z-calculations to be performed without having to access an external z-buffer via the memory bus. Naturally, this eliminates the expensive z-buffer reads and writes that occur constantly on immediate mode renderers.
Rendering small tiles instead of a complete scene also means that pixels that are not visible can be thrown out before the rendering process beings. Since each tile consists of a display list that includes each polygon in that tile, hidden surface removal can occur before any textures are applied. Once again this significantly reduces the amount of information that must travel over the memory bus, as textures for non-visible surfaces do not need to be processed. Also located on chip is a tile buffer which acts as a fame buffer for an individual tile. This allows blending to be performed without costly memory reads and writes.
With all the benefits associated with a tile based renderer, one may wonder why every graphics processor out there does not utilize this method of rendering. In most cases, it is the amount of work required to get a tile based renderer working that keeps a product from being produced. Designing a tile based renderer requires a completely different chip design compared to immediate mode renderers. Even Imagination has experienced their share of problems with early tile based rendering chips. Luckily, it seems that after some trial and error, they have tile based rendering down on the Kyro II chip.
Instead of going completely tile based, it seems that the big 3 (3dfx, NVIDIA, and ATI) had been going after hidden surface removal methods of their own. Whether or not these optimizations, which have been focused around the z-buffer, will provide the bandwidth relief that is needed is still up in the air. If you ask NVIDIA or ATI, they will claim that optimizations are the way to go. Imagination, on the other hand, says there is no way that these optimizations can compare to the memory bandwidth savings provided by a tile based architecture.
Despite the advantages that a tile based system offers, the method has come under fire recently. Most notably, the lead programmer at Epic Games, Tim Sweeney, recently mentioned that implementing a T&L subsystem on a tile based renderer was next to impossible.
We approached STMicroelectroncis, the producer of the Kyro II chip, and asked them their response to the statement. They assured us that the idea that T&L support on a tile based rendering platform is not possible is completely untrue. In addition, the folks at STMicroelectronics said that they have a meeting with Tim at GDC, hinting that they will prove Tim incorrect with a demonstration of a tile based system with T&L. Note, however, that the Kyro II still lacks T&L support.