With ALi boasting support for the 100MHz Frontside Bus and a large cacheable memory area, how could VIA resist but to release a Super7 candidate of their own? Originally, the VIA VP3 was expected to be the very first 100MHz + Socket-7 + AGP motherboard, unfortunately VIA dropped a bombshell on the market by announcing that the VP3 wouldn't support any bus speeds greater than 66MHz. At the same time VIA hinted at a Mobile-VP3 chipset, the MVP3, that would actually support the 100MHz bus speed & AGP. Now, under a year later, the MVP3 chipset is almost ready to make its grand-entrance, how grand will it be? We can only speculate.
In spite of the name, the Mobile VP3 can be used in both Desktop and Mobile motherboard solutions, this versatility will prove to be beneficial for VIA since no other chipset manufacturer has a chipset that will officially run the 100MHz on a Notebook system. In the desktop arena, the MVP3 will definitely be a competitor to the Aladdin V by ALi, with both chipsets supporting all of the features the Intel TX chipset does adding support for a 100MHz Frontside bus, as well as AGP 2x support. The MVP3 differs from the Aladdin V in two major areas, both involving RAM...let's explore the two differences.
While the Aladdin V only supports EDO, FPM, and SDRAM, the MVP3 supports JEDEC BDDR SDRAM-II (Bi Directional Double Data Rate SDRAM), Virtual Channel SDRAM, and Enhanced SDRAM. While those last few SDRAM types are next to impossible to come across that may change if the demand for SDRAM-II modules increases, possibly by the success of a chipset that supports the standard. Its a heavy weight to put on the MVP3's unreleased shoulders, but it is there nevertheless.
Speaking of RAM, the MVP3 chipset introduces a unique feature into the Super7 arena, the ability to run the Memory Bus Speed at 66MHz, while using a 100MHz Bus Speed to derive the Processor Clock. This means that, in theory, you could even re-use your old generic 60ns EDO SIMMs on a MVP3 motherboard. Not a bad feature for VIA to include.
The only other real difference between the MVP3 and the Aladdin V is that the MVP3 doesn't feature any Internal L2 cache bits/Tag RAM bits, making high quality L2 cache with a fast Tag RAM chip a necessity for all MVP3 boards if you plan on using them with the 100MHz bus speed. This introduces a new factor into achieving system stability, L2 cache quality, if a manufacturer of a MVP3 motherboard decides to skimp on the L2 cache and include 8 or even 10ns SRAM chips, expect to have problems galore at 100MHz.
An interesting note, unlike all previous VIA Socket-7 chipsets, the MVP3 only features an integrated 8-bit Tag comparator while the VP2 for example features an integrated 10-bit Tag comparator. Translation? Don't expect MVP3 motherboards to be able to cache the supported 1GB of RAM, in combination with the L2 cache sizes and Tag RAM chips that will be used on most MVP3 motherboards, expect cacheable memory areas to range from 256MB down to 64MB. While waiting for an official word from VIA on this issue, it seems highly unlikely that MVP3 motherboards will be able to compete with Aladdin V boards in terms of cacheable memory areas.
Performance wise, in spite of the fewer CPU-to-DRAM write buffers, the MVP3 should be on the heels of the Aladdin V, outperforming the Intel TX chipset at the 66MHz bus speed and leaving it behind when clocked at 100MHz.
VIA has been in the lime light of the chipset industry for much longer than Acer Labs has, so it'll take quite a bit for VIA to throw in the towel in the Super7 battle. Expect the MVP3 to be the Aladdin V's biggest competitor, in the end it will most likely come down to a battle among motherboard manufacturers to completely harness the immense power of one of these two chipsets.
|VIA VT82C Apollo Mobile VP3 Chipset|
|Common Name||Apollo MVP3|
|Chipset Packaging||Number of chips||2 (VT82C598AT System Controller, VT82C586B PCI-to-ISA Bridge)|
|Packaging Type||1 x 476-pin BGA; 1 x 208-pin QFP|
|CPU Support||Number of CPUs||1|
|AMD CPUs Supported||K5, K6, K6-3D|
|Cyrix CPUs Supported||6x86 (M1), 6x86MX (M2) w/ Linear Burst Mode Support|
|Intel CPUs Supported||Pentium, Pentium MMX|
|Cache||Type||Synchronous Pipeline Burst Cache|
|Maximum Supported Size||2048KB|
|Maximum Cacheable DRAM Area||???|
|Memory||Maximum DRAM Supported||1GB|
|BEDO DRAM Read Timings (66MHz)||N/A|
|EDO DRAM Read Timings (66MHz)||5-2-2-2|
|FPM DRAM Read Timings (66MHz)||5-3-3-3|
|SDRAM Read Timings (66MHz)||3-1-1-1|
|Data Path to Memory||64-bits|
|Hard Disk Controller||Chip||VIA BMIDE Controller (VT82C586B)|
|Max. Theoretical Transfer Rate||PIO Mode 5/DMA Mode 3 (33.3MB/S)|
|PCI Interface||Supported PCI Bus Speeds||25, 30, 33 MHz|
|Async. PCI Bus Speed||Yes (Pseudo Synchronous)|
|PCI Specification||2.1 (66 MHz max.)|
|Power Management||PC97 Compliance||Yes|
|Suspend to Disk||Yes|
|HDD Power Down||Yes|
|Unified Memory Architecture||No|
|Peripheral Support||USB Support||Yes|
|Plug and Play Port||Yes|
|Write Buffers||CPU-to-DRAM||16 QWords|
|Officially Supported Bus Speeds||50, 60, 66, 75, 83, 100 MHz|
|Unofficially Achieved Bus Speeds||Unknown|