More Than Just a Die Shrink

It is true that if the Samuel2 core was simply a die shrink of the Samuel core then chip price could be dramatically reduced, as the chip would have the same complexity on a smaller die. The Samuel2 is more than just a die shrink however, as VIA decided to add an additional 64KB of L2 cache, raising the L2 cache level from 0KB on the original Samuel to 64KB on the Samuel2.

Naturally, the addition of on die L2 cache helps to improve the Samuel2 speed. As we saw with the change of the Celeron core from the original Covington core to the Mendocino and now Coppermine128 cores, the addition of L2 cache can make a big difference. The cache, much like the Duron and Thunderbird's cache, is exclusive, meaning that the L1 cache is not duplicated in the L2 cache. With such a large L1 cache, inclusive cache on the Samuel2 core would essentially render the L2 cache useless as it would constantly be filled with information from the L1.

It is only the addition of the extra 64KB L2 cache and the fab shrink to 0.15 micron that distinguishes the Samuel core from the Samuel2 core. The chip continues to include both MMX and 3Dnow! optimizations found on the original Samuel core and contains the same 12 stage pipeline. The pipeline contains far fewer stages than the Pentium 4's 20 stage pipeline, but does contain the same number of stages as the popular AMD Duron processor.

The bus speed of the Samuel2 remains the same as the bus speed used by the original Samuel core, meaning that the Samuel2 Cyrix III chip will run at both 100 and 133 MHz bus speeds. This is quite a step up from the 66 MHz bus speed on Intel's budget Celeron chip and falls behind the AMD Duron's 100 MHz DDR bus speed (200 MHz effective). This may provide a point of confusion, however, as a 700 MHz Cyrix III running on the 100 MHz bus could actually be slower than the 667 MHz chip that we are looking at today that runs on a 133 MHz bus.

The final slight change that accompanies the new Cyrix III come with the package in which the new Samuel2 based Cyrix III will be delivered. Just like its predecessor, the Samuel2 based Cyrix III will fit in any Socket 370 motherboard and will work in many standard Socket 370 motherboards with a BIOS update. However, this time around the Cyrix III will be available in both a CPGA (ceramic pin grid array) as well as a PPGA (plastic pin grid array) package.

The table below shows a quick summary of the Samuel2 Cyrix III, as well as the original Samuel Cyrix III and competing products from Intel and AMD.

CPU Specification Comparison
 
AMD Duron
Intel Celeron
VIA Cyrix III
Core
Spitfire
Mendocino
Coppermine128
Samuel
Samuel2

Clock Speed

600 - 800 MHz
300 - 533 MHz
533 - 800MHz
500 - 667 MHz
667 MHz +
L1 Cache
128KB
32KB
128KB
128KB
L2 Cache
64KB
128KB
0KB
64KB
L2 Cache Speed
core clock
core clock
core clock
L2 Cache bus
64-bit
64-bit
256-bit
N/A
?
System Bus
100 MHz DDR (200 MHz effective) EV6
66 MHz GTL+ / 100 MHz (800 MHz only)
100 - 133 MHz GTL+
Interface
Socket-A
Slot-1
Socket-370
Socket-370
Socket-370
Manufacturing Process
0.18 micron
0.25 micron
0.18 micron
0.18 micron
0.15 micron
Die Size
100mm^2
153mm^2
106mm^2
75mm^2
52mm^2
Transistor Count
25 million
19 million
28 million
11 million
15 million

That pretty much covers the technical side of the Samuel2 incarnation of the Cyrix III. Let's find out if the changes VIA made are enough to raise the Cyrix III from the grave.

The Samuel2 Core The Test

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