The revenge of AMD Barcelona's TLB?by Johan De Gelas on March 17, 2008 11:00 AM EST
- Posted in
- IT Computing general
- Low latency L1 TLB (Data and Instructions) 48 entries, supporting all pagesizes
- L2 TLB (Data and Instructions): 512 4k entries, or 128 2M entries
If you compare this with the Intel Penryn family:
- One instruction TLB: 128 entries (4 KB) but only 8 entries for 2MB pages.
- The Data TLB has 2 levels:
– 16 entries (4 KB)
– 256 entries (4 KB), but only 32 for larger pages(2 MB)
You can see that AMD’s K10 family has really massive TLBs compared to the Penryn and previous Intel CPUs, especially if you want to run with large pages. So while this will certainly not affect anyone behind a desktop or mobile, it may well have an impact in the serverworld.
VMWare 3.5 does not yet support Nested Paging, it will be present in an upcoming update. This kind of paging requires really massive TLBs as the page tables of each guest OS are cached in the TLB. But even with shadowpaging, having big TLBs should help when you have a lot of VMs running.
We still have to do quite a bit of benchmarking, but it is clear that the TLB architecture of Barcelona deserves some positive light too. It will be very interesting to see what kind of TLB architecture Nehalem will have, as Nehalem will be the first to support Intel’s Extended Page Tables (EPT, Intel’s version of Nested Pages).
It is interesting to note that Nehalem has a NEW second level 512 entry TLB…