Nehalem: Single die, 8-cores, 731M transistors, 16 threads, memory controller, graphics, amazing.

Intel announced that in its largest configuration, Nehalem (2H 2008, 45nm) will feature 8 cores on a single die, each core supporting 2 threads per core (welcome back Hyper Threading) for a total of 16 threads per physical chip.

The Nehalem design is now complete, it was finished about a month ago, and Intel had a wafer of Nehalem at its 10-year anniversary IDF.

Each 4-core Nehalem is built from 731M transistors, nearly double that of Penryn. The 8-core variant isn't ready yet so we don't have a transistor count for that one as of this writing. Nehalem will sport an on-die memory controller and a new system interconnect called Intel's QuickPath Interconnect (Intel's answer to Hyper Transport).

Nehalem is fully expected to close the gap between AMD and Intel when it comes to memory performance and multi-processor scalability.

In its usual fashion, Intel demonstrated a fully functional Nehalem based on silicon that's only 3 weeks old. The silicon is booting both Windows XP and OS X, although we only saw the XP demo.

Index 10x power reduction by 2010, err 2008


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  • strikeback03 - Thursday, September 20, 2007 - link

    Which temperature units is that "160 below 0" in? Reply
  • amdsupport - Tuesday, September 18, 2007 - link


    Intel didn't have much to say about the architecture other than it was called Kenmore and we'd see it in 2008 in the Consumer Electronics market.

    Did Sears/Kmart design part of the chip also? :p
    seems like intel could come up with a more creative name than that.

    I'm kinda curious though what consumer electronics will end up with some form of this.
  • cheburashka - Tuesday, September 18, 2007 - link

    The believe the codename is actually Canemore. Reply
  • AmberClad - Tuesday, September 18, 2007 - link

    I did a double take when I saw that too. I couldn't believe the PR people let that one through. This is what happens when you randomly pick the name of a city, without considering the alternate connotations of that name. Reply
  • strikeback03 - Thursday, September 20, 2007 - link

    I was wondering if it was intended as a joke that an architecture designed for the CE market is given the same name as a CE company. Reply
  • JarredWalton - Tuesday, September 18, 2007 - link

    Code names are not product names. They could call something "AMD- Thunderbird" internally if they wanted; it's only the final product names that really matter in terms of trademarks. Reply
  • bespoke - Wednesday, September 19, 2007 - link

    In the mid nineties, Apple got in trouble for a product with a code name of "Sagan". Carl Sagan's lawyers made a stink about Apple's use of his name, even thought it was an internal code name. Apple engineers changed the code name to "BHA", which was understood to mean "butt-head astronomer". Sagan sued for libel after that. :) Reply
  • archcommus - Tuesday, September 18, 2007 - link

    Looks like current trends will continue for the near future. Both AMD and Intel are heading in similar directions: new architecture on 65 nm, same architecture on 45 nm, and then a brand new architecture that is highly parallel and a large divergence from CPU designs of today. And, just like today, it appears Intel will get to that new architecture at least a half year if not a full year ahead of AMD. Glad to see things accelerating so quickly in the CPU market, as long as AMD DOES keep catching up we should be okay!

    Question: Does having a FSB implementation versus an on-die memory controller have any tangible advantage or disadvantage to the end user besides the impact on memory performance? Which types of applications see this impact the most? It's surprising that I've owned an Athlon 64 for over two years now, and if I upgraded any time before next summer, I'd STILL be going "backwards" regarding that. Wonder why Intel stuck with it for so long.
  • Lord Banshee - Tuesday, September 18, 2007 - link

    I would say you will not see a difference in Mem Performance going from A64->Core2Duo. But if intel does do the IMC then it might allow them to have smaller caches with less performance hit then makes their CPUs cheaper or have more room for other random logic. Reply
  • Shadowmage - Tuesday, September 18, 2007 - link

    Nehalem is definitely NOT 8 cores on a single die. Nehalem is 4 cores on a single die, with possibility for MCP solutions (8 cores on 2 dies). Reply

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