AMD has been unusually quiet since Intel announced their next-generation microprocessor architecture at IDF just a couple of months ago. AMD argued that they didn't have to talk about a new architecture, as Intel is just playing catch-up to their current architecture.

However, we look at it like this - AMD has the clear advantage today, and for a variety of reasons, their stance in the marketplace has not changed all that much. With a more competitive product, Intel could make it very difficult for AMD, which in our minds is even more reason for AMD to put their best foot forward today, letting the world know that when pushed, they will push back.

Regardless of what we think AMD should do, the fact of the matter is that we haven't heard much about what they are going to do, starting even before IDF. Could it be related to the departure of AMD's Fred Weber? We're not entirely certain, but while in Dresden for the Fab 36 grand opening we were able to speak with Phil Hester, AMD's new CTO.

AMD's new CTO - Phil Hester

Phil headlined a briefing on the future of AMD's microprocessor architecture, which piqued our interest, as it promised to answer questions we've had for a good part of the year. The briefing itself was much more of a Q&A, rather than a black and white outline of AMD's plans to counteract Intel's latest offerings. The one concrete piece of information we did get however, was this table below, outlining AMD's current architecture, what's coming very soon, and in the distant future:

Now Coming Soon Future Goals
AMD64 Architecture
Extensions to AMD64 FPU Extensions to AMD64
Dual Core Architecture
Multi-Core Architecture Throughput Architecture
Direct Connect Architecture
Scalable SMP Architecture On-chip Coprocessors
Enhanced Virus Protection
Pacifica Virtulization Secure Execution
HyperTransport 1.0 and 2.0
HyperTransport 3.0 HyperTransport 4.0
AMD PowerNow! Technology
Partitioned AMD PowerNow! Technology System Resource Management
High Reliability RAS
Mainframe-class Reliability Best-in-class Reliability
System Performance
System Performance per Watt Throughput per Watt per Dollar

Note that the "Now" column does include a bit of what's coming soon, mainly support for DDR2. As we've mentioned before, DDR2 support is due for the Athlon 64 next year, along with the upcoming Socket M2 (940-pins) for the desktop and Socket F (1207-pins) for servers. Note that despite the similarity of the M2 socket to the first K8 socket, it will not be pin compatible with current Opterons and/or older Athlon 64s.

The Coming Soon column refers to features that could begin appearing as early as the next twelve months, but obviously items like DDR3 will not be shipping in the next year. Both the Coming Soon and Future Goals columns list extensions to the AMD64 instruction set as things coming down the pipe for AMD's architecture. The idea behind extensions to the AMD64 ISA is to improve performance in specific applications, much like how SSE/SSE2/SSE3 have done in the past.

It is no surprise that talks of multi-core are up next, although the desktop will remain predominantly dual core for the foreseeable future. AMD has often talked about a quad core Opteron, and we'd expect to see the first examples of that definitely by the time 65nm rolls around, although AMD has refused to comment as to whether or not we'd see a quad core 90nm Opteron.

In the next year or so AMD plans on truly showcasing the scalability of their Opteron architecture by providing platforms with support for up to 32-socket configurations, truly stressing the scalability of AMD's Direct Connect architecture.

Virtualization support is another common theme for upcoming AMD architectures, but once again this is no big surprise.

When referring to the future goals for AMD's architecture, the only example Phil Hester provided for FPU Extensions to AMD64 was the idea of introducing extensions that would accelerate 3D rendering. We got the impression that these extensions would be similar to a SSEn type of extension, but more specifically focused on usage models like 3D rendering.

Through the use of extensions to the AMD64 architecture, Hester proposed that future multi-core designs may be able to treat general purpose cores as almost specialized hardware, but refrained from committing to the use of Cell SPE-like specialized hardware in future AMD microprocessors. We tend to agree with Hester's feelings on this topic, as he approached the question from a very software-centric standpoint; the software isn't currently asking for specialized hardware, it is demanding higher performance general purpose cores, potentially augmented with some application specific instructions.

Obviously, as AMD's microprocessors get faster, wider and more powerful, faster interconnects (HyperTransport 4.0) and memory buses (DDR4/FBD2) are always necessary.

Hester also reaffirmed AMD's decision to produce a mobile-specific microprocessor architecture sometime in the future, much like what Intel did with the Pentium M. AMD is still probably years away from a shipping product, but the design teams are currently in a specification defining stage with regards to the project. So while Turion 64 today is hardly anything more than a rebadged Athlon 64 with a tweaked manufacturing process, there is continued support for Turion 64 to grow to be much different than its desktop counterpart.

We also asked Phil what his thoughts were with regards to CMOS based voltage regulators on-package, similar to what Intel demonstrated a couple of months ago at IDF. Much to our surprise, Phil talked about it being prohibitively expensive, and that the expertise required to manufacturer a voltage regulator in CMOS is very different than a microprocessor, thus it's not incredibly easy either. So while Hester didn't completely rule it out as an option, he did not seem nearly as gung-ho about it as Intel did at IDF. Intel did preemptively counter Hester's arguments back at IDF, saying that once you got the voltage regulation into silicon that you could drive costs down through mass production, and the normal scaling associated with Moore's Law.

While it was nice to see some sort of an idea of future direction for AMD, Hester didn't provide us with much more in the way of specifics. We couldn't help but feel that he was holding back on a lot of information, which has been the case with AMD for a lot of recent history. On the flip side, AMD's products are still incredibly competitive, and Intel's next-generation microarchitecture won't make its shipping debut until the second half of next year. That's a great deal of time for AMD to continue to rest on the success of the Athlon 64 and Opteron architectures, and hopefully more than enough time for AMD to give us something more concrete on what is coming.

We want roadmaps, with firm dates and code names and features, and we've yet to see or hear it. So the best we can report today, is what we told you back at IDF: with the exception of some minor updates as well as the migration to DDR2, the Athlon 64 micro-architecture will remain unchanged throughout 2006.



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  • erinlegault - Monday, October 17, 2005 - link


    We want roadmaps, with firm dates and code names and features, and we've yet to see or hear it. So the best we can report today, is what we told you back at IDF: with the exception of some minor updates as well as the migration to DDR2, the Athlon 64 micro-architecture will remain unchanged throughout 2006.

    I don't. We are all convinced that AMD has a superior product. Intel claims during IDF are just a marketing ploy.

    For AMD to remain ahead and competitive I don't think it is in their best interests to reveal any information to far ahead of time. Because, with Intels huge source of money and man power, they can probably come up with a counter product before AMD can.

    Intel's recent dual core processors are a perfect example. Intel didn't have dual core on their books, but once AMD was getting close, they designed a new chipset to support their "glued" processors and developed the technology to "glue" to processors together.

    If AMD put a time frame on DDR3, or anything else, Intel would probably beat them to it.
  • Quanticles - Saturday, October 15, 2005 - link

    I think people need to keep in mind that AMD is more about engineering and less about marketing. They cant afford to waste time on features they dont think are important.

    Intel keeps changing their architecture, but look how it's changing...

    Pentium 3 -> Pentium 4 -> Pentium 4 HT -> Pentium 3

    AMD just stuck w/ the best solution to begin with and they're not going to waste any effort on unnecessary features.
  • xsilver - Saturday, October 15, 2005 - link

    dude, most people have moved on from thinking that the pentium M is just a p3 souped up
    it has evolved far beyond that
    you just have to understand that all silicone has to have evolved from somewhere.. no chip is designed from scratch

    and jarred, has there been info about hypertransport 2? are there structural changes or just a speed bump from 2000mhz to 2400? 2800?
  • Quanticles - Sunday, October 16, 2005 - link

    What is so different about pentium M? A few extra features like virus protection and SSE3? That doesnt change the raw performance of normal operation.

    They probably took the original P4 fetch stage, if anything.
  • highlandsun - Saturday, October 15, 2005 - link

    While it's true that everything evolves from something earlier, it's also true that Pentium M largely discards the work that went into Pentium 4. P4 is an evolutionary dead-end. Reply
  • mamisano - Saturday, October 15, 2005 - link">HyperTransport Consortium Website

    The most current HyperTransport technology I/O Link Specification is Release 2.0. To previous specifications, HyperTransport Release 2.0 adds three new speed grades: 2.0 GigaTransfers/second, 2.4 GigaTransfers/second and 2.8 GigaTransfers/second. These new speed grades yield a 16 Gigabyte/second, 19.2 Gigabyte/second and 22.4 Gigabyte/second aggregate bandwidth, an improvement of 75 percent as compared to previous 1.x specifications. In addition, HyperTransport Release 2.0 adds to the existing PCI and PCI-X mapping to include a mapping to PCI Express.

    One of the important features of this new specification is that Specification 2.0 devices are fully backward compatible with prior 1.x devices. This means that existing investments in the technology will continue to be leveraged in the future.

    These new capabilities make HyperTransport technology the highest performance, lowest latency chip-to-chip I/O link available today and continue the HyperTransport tradition of interoperability with popular industry technologies.
  • JarredWalton - Saturday, October 15, 2005 - link

    Regarding HT 2 (and 3/4), I don't know anything other than a name. For CPU to CPU communication, a faster HT link could prove useful. Most system communication isn't even coming close to maxing out 1 GHz HT links, though. Reply
  • msiemsen - Saturday, October 15, 2005 - link

    It's sadly ironic that the sponsored link "Dual Core Architecture" in the table in the article goes to the intel website. Reply
  • ksherman - Friday, October 14, 2005 - link

    bet they got it waiting... just waiting for the "ship" button to be pushed... why release it now, when Intel doesnt have much to fight with? if they have been sooooo quiet, makes you wonder what could be waiting under the wings.... Reply
  • xsilver - Friday, October 14, 2005 - link

    actually, I was wondering if they may be waiting for ddr2 to mature enough (eg. higher speeds) in order to bring the m2 socket out...
    I mean, is there any speculation on the increases that ddr2 are going to bring to amd64?
    on ddr1 cas 2@ddr400 = about cas3@ddr500 so if that trend continues for ddr2 quite a bit of bandwidth will be needed to overcome the higher latencies of ddr2.
    is hypertransport 2.0 the only other feature of the m2 socket??

    personally, I'm trying to figure out if its the right time to jump to pci-e yet as i'm holding onto a highend agp system; sockets are changing soon, so i'm trying to hold out.

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