Instruction Sets: Alder Lake Dumps AVX-512 in a BIG Way

One of the big questions we should address here is how the P-cores and E-cores have been adapted to work inside a hybrid design. One of the critical aspects in a hybrid design is if both cores support different levels of instructions. It is possible to build a processor with an unbalanced instruction support, however that requires hardware to trap unsupported instructions and do core migration mid-execution. The simple way to get around this is to ensure that both types of cores have the same level of instruction support. This is what Intel has done in Alder Lake.

In order to get to this point, Intel had to cut down some of the features of its P-core, and improve some features on the E-core. The biggest thing that gets the cut is that Intel is losing AVX-512 support inside Alder Lake. When we say losing support, we mean that the AVX-512 is going to be physically fused off, so even if you ran the processor with the E-cores disabled at boot time, AVX-512 is still disabled.

Intel’s journey with AVX-512 has been long and fragmented. Some workloads can be vectorised – multiple bits of consecutive data all require the same operation, so you can pack them into a single register and perform it all at once with a single instruction. Designed as its third generation of vector instructions (AVX is 128-bit, AVX2 is 256-bit, AVX512 is 512-bit), AVX-512 was initially found on server processors, then mobile, and we found it in the previous version of desktop processors. At the time, Intel stated that by enabling AVX-512 on its processor line from top to bottom, it would encourage greater adoption, and they were leaning hard into this missive.

But that all changes with Alder Lake. Both desktop processors and mobile processors will now have AVX-512 disabled in all scenarios. But the silicon will still be physically present in the core, only because Intel uses the same core in its next generation server processors called Sapphire Rapids. One could argue that if the AVX-512 unit was removed from the desktop cores that they would be a lot smaller, however Intel has disagreed on this point in previous launches. What it means is that for the consumer parts we have some extra dark silicon in the design, which ultimately might help thermals, or absorb defects.

But it does mean that AVX-512 is probably dead for consumers.

Intel isn’t even supporting AVX-512 with a dual-issue AVX2 mode over multiple operations - it simply won’t work on Alder Lake. If AMD’s Zen 4 processors plan to support some form of AVX-512 as has been theorized, even as dual-issue AVX2 operations, we might be in some dystopian processor environment where AMD is the only consumer processor on the market to support AVX-512.

On the E-core side, Gracemont will be Intel’s first Atom processor to support AVX2. In testing with the previous generation Tremont Atom core, at 2.9 GHz it performed similarly to a Haswell 2.9 GHz Celeron processor, i.e. identical in non-AVX2 situations. By adding AVX2, plus fundamental performance increases, we’re told to expect ‘Skylake-like performance’ from the new E-cores. Intel also stated that both the P-core and E-core will be at ‘Haswell-level’ AVX2 support.

By enabling AVX2  on the E-cores, Intel is also integrating support for VNNI instructions for neural network calculations. In the past VNNI (and VNNI2) were built for AVX-512, however this time around Intel has done a version of AVX2-VNNI for both the P-core and E-core designs in Alder Lake. So while AVX-512 might be dead here, at least some of those AI acceleration features are carrying over, albeit in AVX2 form.

For the data center versions of these big cores, Intel does have AVX-512 support and new features for matrix extensions, which we will cover in that section.

Gracemont Microarchitecture (E-Core) Examined Conclusions: Through The Cores and The Atoms
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  • blanarahul - Thursday, August 19, 2021 - link

    That’s Intel Thread Director. Not Intel Threat Detector, which is what I keep calling it all day, or Intel Threadripper, which I have also heard.

    never thought my nerdy interest would make me laugh
    Reply
  • Hifihedgehog - Thursday, August 19, 2021 - link

    One takeaway as far as the rumors we have been operating on are concerned is that Raichu (who has a 90% accuracy rating for his rumors/leaks) would now appear to have been wrong with his recent leak. Sad panda face, I know. I did some analysis elsewhere and here is what I had shared:

    ===

    The information released from Intel seems to invalidate this previous rumor above that I shared some weeks ago.

    The Core i9 11900K operates at a 5.3 GHz single-core boost and gets a score of 623 in Cinebench R20.

    Intel claims a 19% IPC with Golden Cove over Cypress Lake (i.e. Rocket Lake's core microarchitecture). If we see the same single-core boost clock speeds of 5.3 GHz, that would equate to 741. Let's take a huge moment to stare at this astounding achievement. This is nothing to be sneezed at! This puts AMD in a very distant position as far as single-threaded performance is concerned and puts the onus on them to deliver a similar gain with Zen 4. However, switching hats from performance analyst to fact checker, this is in no wise close to the ">810" claim as stated above. To achieve a score of >810, they would need a clock speed of roughly 5.8 GHz (623 points * 1.19 IPC improvement / 5.3 GHz * 5.8 GHz). That, quite frankly, I highly doubt.

    ===

    Link:

    http://forum.tabletpcreview.com/threads/intel-news...

    That said, though, getting roughly 2/3s of the way there to the rumored performance is still a colossal jump for Intel and is minimally going to have AMD in a rather painful position until Zen 4 comes around.
    Reply
  • arayoflight - Thursday, August 19, 2021 - link

    The IPC improvement won't be the same as you can see clearly in the intel provided chart. Some workloads will run slower than Cypress cove and some can go as high as 60%.

    The 19% is an average, indicative figure and is not going to be the same in every benchmark. The >810 might as well be true.
    Reply
  • Wrs - Thursday, August 19, 2021 - link

    The 19% is a median figure. Based on the graphic from Intel, there are tasks that go over 50% faster and tasks that do about the same if not slower than Cypress Cove. How do we know for certain Cinebench is anywhere close to the median? Reply
  • mattbe - Thursday, August 19, 2021 - link

    Where did you see median?/ It says right on the graph that the 19% is a geometric mean. Reply
  • mode_13h - Friday, August 20, 2021 - link

    Aside from that, the same point applies. We don't know where Cinebench sits, in the range. Reply
  • Hifihedgehog - Friday, August 20, 2021 - link

    As a very standard rule, though, Cinebench (especially the latest R20 and R23 iterations) have tracked very closely to the mean IPC scores that Intel and AMD have advertised for the last few years. Reply
  • mode_13h - Saturday, August 21, 2021 - link

    Does R20 use AVX-512, though? Reply
  • Spunjji - Monday, August 23, 2021 - link

    @mode_13h: Yes, Cinebench R20 makes use of AVX-512. It's why some of the more AMD-flavoured commentators around the interwebs insisted that R15 was the /correct/ Cinebench to use for comparisons.

    Personally I think it was a good example of the AVX-512 benefit in the "real world", i.e. it's there but not as substantial as Intel's pet benchmarks imply.

    That aside, the lack of AVX-512 on ADL is another data point that suggests Raichu's R20 leak may have been highly optimistic. I always though it sounded a bit much.
    Reply
  • mode_13h - Tuesday, August 24, 2021 - link

    > Yes, Cinebench R20 makes use of AVX-512.

    Good to know. Thanks, as always!
    Reply

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