SPEC - Single-Threaded Performance

Single-thread performance of server CPUs usually isn’t the most important metric for most scale-out workloads, but there are use-cases such as EDA tools which are pretty much single-thread performance bound.

Power envelopes here usually don’t matter, and what is actually the performance factor that comes at play here is simply the boost clocks of the CPUs as well as the IPC improvement, and memory latency of the cores. 

The one hiccup for the Xeon 8380 this generation is the fact that although there’s plenty of IPC gains to be had compared to previous microarchitectures, the new SKU is only boosting up to 3.4GHz, whereas the 8280 was able to boost up to 4GHz, which is a 15% deficit.

SPECint2017 Rate-1 Estimated Scores

Even with the clock frequency disadvantage, thanks to the IPC gains, much improved memory bandwidth, as well as the much larger L3 cache, the new Ice Lake part to most of the time beat the Cascade Lake part, with only a couple of compute-bound core workloads where it falls behind.

SPECfp2017 Rate-1 Estimated Scores

The floating-point figures are more favourable to the ICX architecture due to the stronger memory performance.

SPEC2017 Rate-1 Estimated Total

Overall, the new Xeon 8380 at least manages to post slight single-threaded performance increases this generation, with larger gains in memory-bound workloads. The 8380 is essentially on par with AMD’s 7763, and loses out to the higher frequency optimised parts.

Intel has a few SKUs which offers slightly higher ST boost clocks of up to 3.7GHz – 300Mhz / 8.8% higher than the 8380, however that part is only 8-core and features only 18MB of cache. Other SKUS offer 3.5-3.6GHz boosts, but again less cache. So while the ST figures here could improve a bit on those parts, it’s unlikely to be significant.

SPEC - Multi-Threaded Performance SPEC - Per-Core Performance under Load
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  • deil - Tuesday, April 6, 2021 - link

    that's a lot of upgrade for intel Reply
  • Gomez Addams - Tuesday, April 6, 2021 - link

    That is a curious-looking wafer. I thought it was fake at first but then I noticed the alignment notch. Actually, I'm still not convinced it's real because I have seen lots and lots of wafers in various stages of production and I have never seen one where partial chips go all the way out to the edges. It's a waste of time to deal with those in the steppers so no one does that. Reply
  • JCB994 - Tuesday, April 6, 2021 - link

    Periphery defects? I used to deal with those...buildup of material that would breakdown during wet processing and stream particles all over the wafer. Running partials as far out as possible helped. Nowadays...do they still use big wet benches? I have been out awhile... Reply
  • Gomez Addams - Tuesday, April 6, 2021 - link

    Yes, they do. That's one of the systems I spent lots of time working on. Those don't look defects to me. They are just a continuation of the chip pattern. Reply
  • Arsenica - Tuesday, April 6, 2021 - link

    It isn´t real if it doesn´t have DrIan bite marks.

    /jk
    Reply
  • ilt24 - Tuesday, April 6, 2021 - link

    @Gomez Addams

    I spent my entire career working in the semiconductor industry, although in IT, and I have seen many wafers from 4" to 12" and printing partial die off the edge of the wafer is quite common.

    check out the pictures in these article:
    https://www.anandtech.com/show/15380/i-ran-off-wit...
    https://www.anandtech.com/show/9723/amd-to-spinoff...

    Reply
  • Kamen Rider Blade - Tuesday, April 6, 2021 - link

    So when are we going to hit 450 mm / 18" waffers?

    Are we ever going to get Hexagonal Die's to maximize possible Yields?

    http://www.semiconductor-today.com/news_items/2020...
    https://semiaccurate.com/2015/05/18/disco-makes-he...

    They can already do that for simple LED's, but trying to bring Hexagonal IC Dies into existence is going to be exciting because there is a theoretical 62.5% increase in Manufactured Dies for a given Waffer Diameter and using Hexagonal IC Dies of a similar/identical area.
    Reply
  • ilt24 - Tuesday, April 6, 2021 - link

    @Kamen Rider Blade - "So when are we going to hit 450 mm / 18" waffers?"

    It seems the desire to move to EUV distracted TSMC, Samsung and Intel who are probably the only companies that were really interested in 450mm.
    Reply
  • saratoga4 - Tuesday, April 6, 2021 - link

    >So when are we going to hit 450 mm / 18" waffers?

    For logic, never since there is little to no advantage to larger wafers. Possibly NAND might use it, but we'll see if its even worth it there.

    >Are we ever going to get Hexagonal Die's to maximize possible Yields?

    Probably not for logic. With reticle sizes getting smaller in the coming nodes, it makes even less sense going forward then it did in the past, and it didn't make much sense then to begin with.
    Reply
  • Lukasz Nowak - Thursday, April 8, 2021 - link

    There's another curious thing about the wafer. There are a lot of dies with just clipped corners. If they shifted the entire pattern to the left or right by a quarter of a die, they would get 6 more good ones. That's 7% more dies for free (90 instead of 84).

    Wouldn't that be worth doing?
    Reply

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